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| author | Robert Khasanov <rob.khasanov@gmail.com> | 2014-12-16 18:24:07 +0000 |
|---|---|---|
| committer | Robert Khasanov <rob.khasanov@gmail.com> | 2014-12-16 18:24:07 +0000 |
| commit | d04cd2fbfe1779bb005c75b99c404f50645e3b6f (patch) | |
| tree | 6e35b3f235ba73ab6389cc2ba71ae9d2a968fc36 /llvm/lib/Target | |
| parent | b42003d2bf015df6417cb3a60ec6a5fee8cc0279 (diff) | |
| download | bcm5719-llvm-d04cd2fbfe1779bb005c75b99c404f50645e3b6f.tar.gz bcm5719-llvm-d04cd2fbfe1779bb005c75b99c404f50645e3b6f.zip | |
[AVX512] Enable integer arithmetic lowering for AVX512BW/VL subsets.
Added lowering tests.
llvm-svn: 224349
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 5 | ||||
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrSSE.td | 2 |
2 files changed, 6 insertions, 1 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index e029b4b13f2..2cd1d12ac7d 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -1546,6 +1546,11 @@ void X86TargetLowering::resetOperationActions() { setOperationAction(ISD::LOAD, MVT::v64i8, Legal); setOperationAction(ISD::SETCC, MVT::v32i1, Custom); setOperationAction(ISD::SETCC, MVT::v64i1, Custom); + setOperationAction(ISD::ADD, MVT::v32i16, Legal); + setOperationAction(ISD::ADD, MVT::v64i8, Legal); + setOperationAction(ISD::SUB, MVT::v32i16, Legal); + setOperationAction(ISD::SUB, MVT::v64i8, Legal); + setOperationAction(ISD::MUL, MVT::v32i16, Legal); for (int i = MVT::v32i8; i != MVT::v8i64; ++i) { const MVT VT = (MVT::SimpleValueType)i; diff --git a/llvm/lib/Target/X86/X86InstrSSE.td b/llvm/lib/Target/X86/X86InstrSSE.td index 9aa6fa09db9..0474bb99b91 100644 --- a/llvm/lib/Target/X86/X86InstrSSE.td +++ b/llvm/lib/Target/X86/X86InstrSSE.td @@ -7187,7 +7187,7 @@ let Constraints = "$src1 = $dst" in { SSE_INTMUL_ITINS_P, 1>; } -let Predicates = [HasAVX] in { +let Predicates = [HasAVX, NoVLX] in { defm VPMULLD : SS48I_binop_rm<0x40, "vpmulld", mul, v4i32, VR128, memopv2i64, i128mem, 0, SSE_PMULLD_ITINS>, VEX_4V; |

