Revert "[mips][microMIPS] Implement CFC*, CTC* and LDC* instructions"

This reverts commit r269176 as it caused test-suite failure.

llvm-svn: 269287

10 files changed, 8 insertions, 190 deletions

diff --git a/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp b/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
index 99cb6dcd436..c77cc47e1af 100644
--- a/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
+++ b/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
@@ -341,10 +341,6 @@ static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn,
                                uint64_t Address,
                                const void *Decoder);
 
-static DecodeStatus DecodeFMemMMR6(MCInst &Inst, unsigned Insn,
-                                   uint64_t Address,
-                                   const void *Decoder);
-
 static DecodeStatus DecodeFMem2(MCInst &Inst, unsigned Insn,
                                uint64_t Address,
                                const void *Decoder);
@@ -357,10 +353,6 @@ static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, unsigned Insn,
                                uint64_t Address,
                                const void *Decoder);
 
-static DecodeStatus DecodeFMemCop2MMR6(MCInst &Inst, unsigned Insn,
-                                       uint64_t Address,
-                                       const void *Decoder);
-
 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst,
                                        unsigned Insn,
                                        uint64_t Address,
@@ -1607,22 +1599,6 @@ static DecodeStatus DecodeFMem(MCInst &Inst,
   return MCDisassembler::Success;
 }
 
-static DecodeStatus DecodeFMemMMR6(MCInst &Inst, unsigned Insn,
-                                   uint64_t Address, const void *Decoder) {
-  int Offset = SignExtend32<16>(Insn & 0xffff);
-  unsigned Base = fieldFromInstruction(Insn, 16, 5);
-  unsigned Reg = fieldFromInstruction(Insn, 21, 5);
-
-  Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg);
-  Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
-
-  Inst.addOperand(MCOperand::createReg(Reg));
-  Inst.addOperand(MCOperand::createReg(Base));
-  Inst.addOperand(MCOperand::createImm(Offset));
-
-  return MCDisassembler::Success;
-}
-
 static DecodeStatus DecodeFMem2(MCInst &Inst,
                                unsigned Insn,
                                uint64_t Address,
@@ -1676,22 +1652,6 @@ static DecodeStatus DecodeFMemCop2R6(MCInst &Inst,
 
   return MCDisassembler::Success;
 }
-
-static DecodeStatus DecodeFMemCop2MMR6(MCInst &Inst, unsigned Insn,
-                                       uint64_t Address, const void *Decoder) {
-  int Offset = SignExtend32<11>(Insn & 0x07ff);
-  unsigned Reg = fieldFromInstruction(Insn, 21, 5);
-  unsigned Base = fieldFromInstruction(Insn, 16, 5);
-
-  Reg = getReg(Decoder, Mips::COP2RegClassID, Reg);
-  Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
-
-  Inst.addOperand(MCOperand::createReg(Reg));
-  Inst.addOperand(MCOperand::createReg(Base));
-  Inst.addOperand(MCOperand::createImm(Offset));
-
-  return MCDisassembler::Success;
-}
 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst,
                                        unsigned Insn,
                                        uint64_t Address,
diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp b/llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
index 5bc453bc3d6..57b087d0006 100644
--- a/llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
+++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
@@ -753,19 +753,6 @@ getMemEncodingMMImm9(const MCInst &MI, unsigned OpNo,
 }
 
 unsigned MipsMCCodeEmitter::
-getMemEncodingMMImm11(const MCInst &MI, unsigned OpNo,
-                      SmallVectorImpl<MCFixup> &Fixups,
-                      const MCSubtargetInfo &STI) const {
-  // Base register is encoded in bits 20-16, offset is encoded in bits 10-0.
-  assert(MI.getOperand(OpNo).isReg());
-  unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups,
-                                       STI) << 16;
-  unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI);
-
-  return (OffBits & 0x07FF) | RegBits;
-}
-
-unsigned MipsMCCodeEmitter::
 getMemEncodingMMImm12(const MCInst &MI, unsigned OpNo,
                       SmallVectorImpl<MCFixup> &Fixups,
                       const MCSubtargetInfo &STI) const {
diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h b/llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h
index 09c4f891869..078e4d7a133 100644
--- a/llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h
+++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h
@@ -183,9 +183,6 @@ public:
   unsigned getMemEncodingMMImm9(const MCInst &MI, unsigned OpNo,
                                 SmallVectorImpl<MCFixup> &Fixups,
                                 const MCSubtargetInfo &STI) const;
-  unsigned getMemEncodingMMImm11(const MCInst &MI, unsigned OpNo,
-                                 SmallVectorImpl<MCFixup> &Fixups,
-                                 const MCSubtargetInfo &STI) const;
   unsigned getMemEncodingMMImm12(const MCInst &MI, unsigned OpNo,
                                  SmallVectorImpl<MCFixup> &Fixups,
                                  const MCSubtargetInfo &STI) const;
diff --git a/llvm/lib/Target/Mips/MicroMips32r6InstrFormats.td b/llvm/lib/Target/Mips/MicroMips32r6InstrFormats.td
index 987abf72711..a7b16d3dbf9 100644
--- a/llvm/lib/Target/Mips/MicroMips32r6InstrFormats.td
+++ b/llvm/lib/Target/Mips/MicroMips32r6InstrFormats.td
@@ -993,35 +993,3 @@ class POOL32B_LWP_SWP_FM_MMR6<bits<4> funct> : MipsR6Inst {
   let Inst{15-12} = funct;
   let Inst{11-0}  = offset;
 }
-
-class LDWC1_SDWC1_FM_MMR6<string instr_asm, bits<6> funct>
-    : MMR6Arch<instr_asm> {
-  bits<5> ft;
-  bits<21> addr;
-  bits<5> base = addr{20-16};
-  bits<16> offset = addr{15-0};
-
-  bits<32> Inst;
-
-  let Inst{31-26} = funct;
-  let Inst{25-21} = ft;
-  let Inst{20-16} = base;
-  let Inst{15-0}  = offset;
-}
-
-class POOL32B_LDWC2_SDWC2_FM_MMR6<string instr_asm, bits<4> funct>
-    : MMR6Arch<instr_asm>, MipsR6Inst {
-  bits<5> rt;
-  bits<21> addr;
-  bits<5> base = addr{20-16};
-  bits<11> offset = addr{10-0};
-
-  bits<32> Inst;
-
-  let Inst{31-26} = 0b001000;
-  let Inst{25-21} = rt;
-  let Inst{20-16} = base;
-  let Inst{15-12} = funct;
-  let Inst{11}    = 0;
-  let Inst{10-0}  = offset;
-}
diff --git a/llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td b/llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td
index 7fc9dfbc051..a180a570ba7 100644
--- a/llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td
+++ b/llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td
@@ -59,10 +59,6 @@ class BGEZALC_MMR6_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM_MMR6<"bgezalc", 0b110000>,
 class BLEZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<"blezalc", 0b110000>,
                          MMDecodeDisambiguatedBy<"BlezGroupBranchMMR6">;
 class CACHE_MMR6_ENC : CACHE_PREF_FM_MMR6<0b001000, 0b0110>;
-class CFC1_MMR6_ENC : POOL32F_MFTC1_FM_MMR6<"cfc1", 0b01000000>;
-class CFC2_MMR6_ENC : POOL32A_MFTC2_FM_MMR6<"cfc2", 0b1100110100>;
-class CTC1_MMR6_ENC : POOL32F_MFTC1_FM_MMR6<"ctc1", 0b01100000>;
-class CTC2_MMR6_ENC : POOL32A_MFTC2_FM_MMR6<"ctc2", 0b1101110100>;
 class CLO_MMR6_ENC : POOL32A_2R_FM_MMR6<0b0100101100>;
 class CLZ_MMR6_ENC : SPECIAL_2R_FM_MMR6<0b010000>;
 class DIV_MMR6_ENC : ARITH_FM_MMR6<"div", 0x118>;
@@ -78,8 +74,6 @@ class JIALC_MMR6_ENC : JMP_IDX_COMPACT_FM<0b100000>;
 class JIC_MMR6_ENC   : JMP_IDX_COMPACT_FM<0b101000>;
 class JRC16_MMR6_ENC: POOL16C_JALRC_FM_MM16R6<0x3>;
 class JRCADDIUSP_MMR6_ENC : POOL16C_JRCADDIUSP_FM_MM16R6<0x13>;
-class LDC1_MMR6_ENC : LDWC1_SDWC1_FM_MMR6<"ldc1", 0b101111>;
-class LDC2_MMR6_ENC : POOL32B_LDWC2_SDWC2_FM_MMR6<"ldc2", 0b0010>;
 class LSA_MMR6_ENC : POOL32A_LSA_FM<0b001111>;
 class LWP_MMR6_ENC : POOL32B_LWP_SWP_FM_MMR6<0x1>;
 class LWPC_MMR6_ENC  : PCREL19_FM_MMR6<0b01>;
@@ -681,15 +675,6 @@ class MTC2_MMR6_DESC_BASE<string opstr, RegisterOperand DstRC,
   Format f = FrmFR;
   string BaseOpcode = opstr;
 }
-class CFC2_MMR6_DESC_BASE<string opstr, RegisterOperand DstRC,
-                          RegisterOperand SrcRC, SDPatternOperator OpNode = null_frag> {
-  dag InOperandList = (ins SrcRC:$impl);
-  dag OutOperandList = (outs DstRC:$rt);
-  string AsmString = !strconcat(opstr, "\t$rt, $impl");
-  list<dag> Pattern = [(set DstRC:$rt, (OpNode SrcRC:$impl))];
-  Format f = FrmFR;
-  string BaseOpcode = opstr;
-}
 
 class MTC0_MMR6_DESC : MTC0_MMR6_DESC_BASE<"mtc0", COP0Opnd, GPR32Opnd>;
 class MTC1_MMR6_DESC : MTC1_MMR6_DESC_BASE<"mtc1", FGR32Opnd, GPR32Opnd,
@@ -743,48 +728,6 @@ class MFHC1_D64_MMR6_DESC : MFC1_MMR6_DESC_BASE<"mfhc1", GPR32Opnd, FGR64Opnd,
                                                 II_MFHC1>, HARDFLOAT, FGR_64;
 class MFHC2_MMR6_DESC : MFC2_MMR6_DESC_BASE<"mfhc2", GPR32Opnd, COP2Opnd>;
 
-class CFC1_MMR6_DESC : MTC1_MMR6_DESC_BASE<"cfc1", GPR32Opnd, CCROpnd, II_CFC1>,
-                       HARDFLOAT;
-class CFC2_MMR6_DESC : CFC2_MMR6_DESC_BASE<"cfc2", GPR32Opnd, COP2Opnd>;
-class CTC1_MMR6_DESC : MTC1_MMR6_DESC_BASE<"ctc1", CCROpnd, GPR32Opnd, II_CTC1>,
-                       HARDFLOAT;
-class CTC2_MMR6_DESC : MTC2_MMR6_DESC_BASE<"ctc2", COP2Opnd, GPR32Opnd>;
-
-class LDWC1_DESC_BASE<string opstr, RegisterOperand RC, InstrItinClass Itin,
-                      SDPatternOperator OpNode = null_frag> : MipsR6Inst,
-                      HARDFLOAT {
-  dag InOperandList = (ins mem_mm_16:$addr);
-  dag OutOperandList = (outs RC:$ft);
-  string AsmString = !strconcat(opstr, "\t$ft, $addr");
-  list<dag> Pattern = [(set RC:$ft, (OpNode addrDefault:$addr))];
-  Format f = FrmFI;
-  InstrItinClass Itinerary = Itin;
-  string BaseOpcode = opstr;
-  bit mayLoad = 1;
-  let DecoderMethod = "DecodeFMemMMR6";
-}
-class LDC1_D32_MMR6_DESC : LDWC1_DESC_BASE<"ldc1", AFGR64Opnd, II_LDC1, load>,
-                           FGR_32;
-class LDC1_D64_MMR6_DESC : LDWC1_DESC_BASE<"ldc1", FGR64Opnd, II_LDC1, load>,
-                           FGR_64;
-
-class COP2LD_MMR6_DESC_BASE<string opstr, RegisterOperand COPOpnd,
-                            InstrItinClass Itin,
-                            SDPatternOperator OpNode = null_frag> {
-  dag OutOperandList = (outs COPOpnd:$rt);
-  dag InOperandList = (ins mem_mm_11:$addr);
-  string AsmString = !strconcat(opstr, "\t$rt, $addr");
-  list<dag> Pattern = [(set COPOpnd:$rt, (OpNode addrDefault:$addr))];
-  Format f = FrmFI;
-  InstrItinClass Itinerary = Itin;
-  string BaseOpcode = opstr;
-  bit mayLoad = 1;
-  string DecoderMethod = "DecodeFMemCop2MMR6";
-}
-
-class LDC2_MMR6_DESC : COP2LD_MMR6_DESC_BASE<"ldc2", COP2Opnd, NoItinerary,
-                                             load>;
-
 /// Floating Point Instructions
 class FARITH_MMR6_DESC_BASE<string instr_asm, RegisterOperand RC,
                             InstrItinClass Itin, bit isComm,
@@ -1240,10 +1183,6 @@ def BNEZALC_MMR6 : R6MMR6Rel, BNEZALC_MMR6_ENC, BNEZALC_MMR6_DESC,
                    ISA_MICROMIPS32R6;
 def BREAK_MMR6 : StdMMR6Rel, BRK_MMR6_DESC, BRK_MMR6_ENC, ISA_MICROMIPS32R6;
 def CACHE_MMR6 : R6MMR6Rel, CACHE_MMR6_ENC, CACHE_MMR6_DESC, ISA_MICROMIPS32R6;
-def CFC1_MMR6 : StdMMR6Rel, CFC1_MMR6_DESC, CFC1_MMR6_ENC, ISA_MICROMIPS32R6;
-def CFC2_MMR6 : StdMMR6Rel, CFC2_MMR6_ENC, CFC2_MMR6_DESC, ISA_MICROMIPS32R6;
-def CTC1_MMR6 : StdMMR6Rel, CTC1_MMR6_DESC, CTC1_MMR6_ENC, ISA_MICROMIPS32R6;
-def CTC2_MMR6 : StdMMR6Rel, CTC2_MMR6_ENC, CTC2_MMR6_DESC, ISA_MICROMIPS32R6;
 def CLO_MMR6 : R6MMR6Rel, CLO_MMR6_ENC, CLO_MMR6_DESC, ISA_MICROMIPS32R6;
 def CLZ_MMR6 : R6MMR6Rel, CLZ_MMR6_ENC, CLZ_MMR6_DESC, ISA_MICROMIPS32R6;
 def DIV_MMR6 : R6MMR6Rel, DIV_MMR6_DESC, DIV_MMR6_ENC, ISA_MICROMIPS32R6;
@@ -1262,15 +1201,6 @@ def JIC_MMR6 : R6MMR6Rel, JIC_MMR6_ENC, JIC_MMR6_DESC, ISA_MICROMIPS32R6;
 def JRC16_MMR6 : R6MMR6Rel, JRC16_MMR6_DESC, JRC16_MMR6_ENC, ISA_MICROMIPS32R6;
 def JRCADDIUSP_MMR6 : R6MMR6Rel, JRCADDIUSP_MMR6_DESC, JRCADDIUSP_MMR6_ENC,
                       ISA_MICROMIPS32R6;
-def LDC1_D32_MMR6 : StdMMR6Rel, LDC1_D32_MMR6_DESC, LDC1_MMR6_ENC,
-                    ISA_MICROMIPS32R6;
-let DecoderNamespace = "MicroMips32r6FP64" in {
-  def LDC1_D64_MMR6 : StdMMR6Rel, LDC1_D64_MMR6_DESC, LDC1_MMR6_ENC,
-                      ISA_MICROMIPS32R6 {
-    let BaseOpcode = "LDC164";
-  }
-}
-def LDC2_MMR6 : StdMMR6Rel, LDC2_MMR6_ENC, LDC2_MMR6_DESC, ISA_MICROMIPS32R6;
 def LSA_MMR6 : R6MMR6Rel, LSA_MMR6_ENC, LSA_MMR6_DESC, ISA_MICROMIPS32R6;
 def LWP_MMR6 : StdMMR6Rel, LWP_MMR6_ENC, LWP_MMR6_DESC, ISA_MICROMIPS32R6;
 def LWPC_MMR6 : R6MMR6Rel, LWPC_MMR6_ENC, LWPC_MMR6_DESC, ISA_MICROMIPS32R6;
@@ -1582,9 +1512,3 @@ def : MipsPat<(store GPRMM16:$src, addrimm4lsl2:$addr),
               (SW16_MMR6 GPRMM16:$src, addrimm4lsl2:$addr)>, ISA_MICROMIPS32R6;
 def : MipsPat<(subc GPR32:$lhs, GPR32:$rhs),
               (SUBU_MMR6 GPR32:$lhs, GPR32:$rhs)>, ISA_MICROMIPS32R6;
-
-// Patterns for load with a reg+imm operand.
-let AddedComplexity = 41 in {
-  def : LoadRegImmPat<LDC1_D64_MMR6, f64, load>, FGR_64;
-  def : LoadRegImmPat<LDC1_D32_MMR6, f64, load>, FGR_32;
-}
diff --git a/llvm/lib/Target/Mips/MicroMipsInstrFPU.td b/llvm/lib/Target/Mips/MicroMipsInstrFPU.td
index 6357b8c5408..3208f2b9f89 100644
--- a/llvm/lib/Target/Mips/MicroMipsInstrFPU.td
+++ b/llvm/lib/Target/Mips/MicroMipsInstrFPU.td
@@ -20,6 +20,7 @@ def FSUB_MM  : MMRel, ADDS_FT<"sub.d", AFGR64Opnd, II_SUB_D, 0, fsub>,
 def LWC1_MM : MMRel, LW_FT<"lwc1", FGR32Opnd, II_LWC1, load>, LW_FM_MM<0x27>;
 def SWC1_MM : MMRel, SW_FT<"swc1", FGR32Opnd, II_SWC1, store>,
               LW_FM_MM<0x26>;
+def LDC1_MM : MMRel, LW_FT<"ldc1", AFGR64Opnd, II_LDC1, load>, LW_FM_MM<0x2f>;
 def SDC1_MM : MMRel, SW_FT<"sdc1", AFGR64Opnd, II_SDC1, store>,
               LW_FM_MM<0x2e>;
 def LWXC1_MM : MMRel, LWXC1_FT<"lwxc1", FGR32Opnd, II_LWXC1, load>,
@@ -146,10 +147,4 @@ let AdditionalPredicates = [InMicroMips] in {
              MFC1_FM_MM<0xe0>, ISA_MIPS32R2, FGR_32;
   def MFHC1_MM : MMRel, MFC1_FT<"mfhc1", GPR32Opnd, AFGR64Opnd, II_MFHC1>,
                  MFC1_FM_MM<0xc0>, ISA_MIPS32R2, FGR_32;
-  def LDC1_MM : MMRel, LW_FT<"ldc1", AFGR64Opnd, II_LDC1, load>,
-                LW_FM_MM<0x2f>, FGR_32 {
-    let DecoderNamespace = "MicroMips";
-    let DecoderMethod = "DecodeFMemMMR6";
-    let BaseOpcode = "LDC132";
-  }
 }
diff --git a/llvm/lib/Target/Mips/MicroMipsInstrInfo.td b/llvm/lib/Target/Mips/MicroMipsInstrInfo.td
index 65dc2f4afdc..35f5138701c 100644
--- a/llvm/lib/Target/Mips/MicroMipsInstrInfo.td
+++ b/llvm/lib/Target/Mips/MicroMipsInstrInfo.td
@@ -110,14 +110,6 @@ def mem_mm_9 : Operand<i32> {
   let OperandType = "OPERAND_MEMORY";
 }
 
-def mem_mm_11 : Operand<i32> {
-  let PrintMethod = "printMemOperand";
-  let MIOperandInfo = (ops ptr_rc, simm11);
-  let EncoderMethod = "getMemEncodingMMImm11";
-  let ParserMatchClass = MipsMemSimm11AsmOperand;
-  let OperandType = "OPERAND_MEMORY";
-}
-
 def mem_mm_12 : Operand<i32> {
   let PrintMethod = "printMemOperand";
   let MIOperandInfo = (ops ptr_rc, simm12);
diff --git a/llvm/lib/Target/Mips/Mips32r6InstrInfo.td b/llvm/lib/Target/Mips/Mips32r6InstrInfo.td
index 3280da01e30..8bd7b7be90f 100644
--- a/llvm/lib/Target/Mips/Mips32r6InstrInfo.td
+++ b/llvm/lib/Target/Mips/Mips32r6InstrInfo.td
@@ -756,9 +756,9 @@ let AdditionalPredicates = [NotInMicroMips] in {
 def JIALC : R6MMR6Rel, JIALC_ENC, JIALC_DESC, ISA_MIPS32R6;
 def JIC : R6MMR6Rel, JIC_ENC, JIC_DESC, ISA_MIPS32R6;
 def JR_HB_R6 : JR_HB_R6_ENC, JR_HB_R6_DESC, ISA_MIPS32R6;
+def LDC2_R6 : LDC2_R6_ENC, LDC2_R6_DESC, ISA_MIPS32R6;
 let AdditionalPredicates = [NotInMicroMips] in {
   def LL_R6 : LL_R6_ENC, LL_R6_DESC, ISA_MIPS32R6;
-  def LDC2_R6 : LDC2_R6_ENC, LDC2_R6_DESC, ISA_MIPS32R6;
 }
 def LSA_R6 : R6MMR6Rel, LSA_R6_ENC, LSA_R6_DESC, ISA_MIPS32R6;
 def LWC2_R6 : LWC2_R6_ENC, LWC2_R6_DESC, ISA_MIPS32R6;
diff --git a/llvm/lib/Target/Mips/MipsInstrFPU.td b/llvm/lib/Target/Mips/MipsInstrFPU.td
index 165d853eb98..8e58272dc6e 100644
--- a/llvm/lib/Target/Mips/MipsInstrFPU.td
+++ b/llvm/lib/Target/Mips/MipsInstrFPU.td
@@ -404,19 +404,14 @@ def LWC1 : MMRel, LW_FT<"lwc1", FGR32Opnd, II_LWC1, load>, LW_FM<0x31>;
 def SWC1 : MMRel, SW_FT<"swc1", FGR32Opnd, II_SWC1, store>, LW_FM<0x39>;
 
 let DecoderNamespace = "Mips64" in {
-  let AdditionalPredicates = [NotInMicroMips] in {
-    def LDC164 : StdMMR6Rel, LW_FT<"ldc1", FGR64Opnd, II_LDC1, load>,
-                 LW_FM<0x35>, ISA_MIPS2, FGR_64 {
-      let BaseOpcode = "LDC164";
-    }
-  }
+  def LDC164 : LW_FT<"ldc1", FGR64Opnd, II_LDC1, load>, LW_FM<0x35>, ISA_MIPS2,
+               FGR_64;
   def SDC164 : SW_FT<"sdc1", FGR64Opnd, II_SDC1, store>, LW_FM<0x3d>, ISA_MIPS2,
                FGR_64;
 }
-def LDC1 : MMRel, StdMMR6Rel, LW_FT<"ldc1", AFGR64Opnd, II_LDC1, load>,
-           LW_FM<0x35>, ISA_MIPS2, FGR_32 {
-  let BaseOpcode = "LDC132";
-}
+
+def LDC1 : MMRel, LW_FT<"ldc1", AFGR64Opnd, II_LDC1, load>, LW_FM<0x35>,
+           ISA_MIPS2, FGR_32;
 def SDC1 : MMRel, SW_FT<"sdc1", AFGR64Opnd, II_SDC1, store>, LW_FM<0x3d>,
            ISA_MIPS2, FGR_32;
 
diff --git a/llvm/lib/Target/Mips/MipsInstrInfo.td b/llvm/lib/Target/Mips/MipsInstrInfo.td
index 82bcf758845..0539c544a32 100644
--- a/llvm/lib/Target/Mips/MipsInstrInfo.td
+++ b/llvm/lib/Target/Mips/MipsInstrInfo.td
@@ -1742,7 +1742,7 @@ def LWC2 : LW_FT2<"lwc2", COP2Opnd, NoItinerary, load>, LW_FM<0x32>,
            ISA_MIPS1_NOT_32R6_64R6;
 def SWC2 : SW_FT2<"swc2", COP2Opnd, NoItinerary, store>, LW_FM<0x3a>,
            ISA_MIPS1_NOT_32R6_64R6;
-def LDC2 : StdMMR6Rel, LW_FT2<"ldc2", COP2Opnd, NoItinerary, load>, LW_FM<0x36>,
+def LDC2 : LW_FT2<"ldc2", COP2Opnd, NoItinerary, load>, LW_FM<0x36>,
            ISA_MIPS2_NOT_32R6_64R6;
 def SDC2 : SW_FT2<"sdc2", COP2Opnd, NoItinerary, store>, LW_FM<0x3e>,
            ISA_MIPS2_NOT_32R6_64R6;