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| author | Tanya Lattner <tonic@nondot.org> | 2010-11-18 22:06:46 +0000 |
|---|---|---|
| committer | Tanya Lattner <tonic@nondot.org> | 2010-11-18 22:06:46 +0000 |
| commit | cd680956505390d0b804dd806bb5e825b812a881 (patch) | |
| tree | 35284a7cfde39f37fd86c6b84d94dd33f6afcf64 /llvm/lib/Target | |
| parent | 2acd1621f44b9e01e5499b8b935eed108310bfbb (diff) | |
| download | bcm5719-llvm-cd680956505390d0b804dd806bb5e825b812a881.tar.gz bcm5719-llvm-cd680956505390d0b804dd806bb5e825b812a881.zip | |
Fix bug in DAGCombiner for ARM that was trying to do a ShiftCombine on illegal types (vector should be split first).
Added test case.
llvm-svn: 119749
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMISelLowering.cpp | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp index 299009b6bde..7e3f98acd9b 100644 --- a/llvm/lib/Target/ARM/ARMISelLowering.cpp +++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp @@ -4985,7 +4985,8 @@ static SDValue PerformShiftCombine(SDNode *N, SelectionDAG &DAG, EVT VT = N->getValueType(0); // Nothing to be done for scalar shifts. - if (! VT.isVector()) + const TargetLowering &TLI = DAG.getTargetLoweringInfo(); + if (!VT.isVector() || !TLI.isTypeLegal(VT)) return SDValue(); assert(ST->hasNEON() && "unexpected vector shift"); |
