diff options
| author | Owen Anderson <resistor@mac.com> | 2010-12-09 21:34:47 +0000 |
|---|---|---|
| committer | Owen Anderson <resistor@mac.com> | 2010-12-09 21:34:47 +0000 |
| commit | cb4d8f2e74173adc9f2e03240dcbc2c0255d1def (patch) | |
| tree | 49d9e9777affd13f4180448a1fc05645bcb6092d /llvm/lib/Target | |
| parent | aca48a5aff6706f5c8251ffd32531cdb37772730 (diff) | |
| download | bcm5719-llvm-cb4d8f2e74173adc9f2e03240dcbc2c0255d1def.tar.gz bcm5719-llvm-cb4d8f2e74173adc9f2e03240dcbc2c0255d1def.zip | |
Use the new IsAligned fixup flag to improve fixup encodings for Thumb2 branches. This is still not perfect,
but it gets many more of them correct than it did previously.
llvm-svn: 121414
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMAsmBackend.cpp | 3 | ||||
| -rw-r--r-- | llvm/lib/Target/ARM/ARMMCCodeEmitter.cpp | 3 |
2 files changed, 4 insertions, 2 deletions
diff --git a/llvm/lib/Target/ARM/ARMAsmBackend.cpp b/llvm/lib/Target/ARM/ARMAsmBackend.cpp index 606437efbb4..7311b4181df 100644 --- a/llvm/lib/Target/ARM/ARMAsmBackend.cpp +++ b/llvm/lib/Target/ARM/ARMAsmBackend.cpp @@ -101,6 +101,7 @@ static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) { case ARM::fixup_arm_ldst_pcrel_12: // ARM PC-relative values are offset by 8. Value -= 4; + // FALLTHROUGH case ARM::fixup_t2_ldst_pcrel_12: { // Offset by 4, adjusted by two due to the half-word ordering of thumb. Value -= 4; @@ -140,7 +141,7 @@ static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) { // Offset by 8 just as above. return 0xffffff & ((Value - 8) >> 2); case ARM::fixup_t2_branch: { - Value = Value - 8; + Value = Value - 6; Value >>= 1; // Low bit is not encoded. uint64_t out = 0; diff --git a/llvm/lib/Target/ARM/ARMMCCodeEmitter.cpp b/llvm/lib/Target/ARM/ARMMCCodeEmitter.cpp index 4d8791c9989..c901831d858 100644 --- a/llvm/lib/Target/ARM/ARMMCCodeEmitter.cpp +++ b/llvm/lib/Target/ARM/ARMMCCodeEmitter.cpp @@ -53,7 +53,8 @@ public: { "fixup_t2_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, { "fixup_arm_adr_pcrel_12", 1, 24, MCFixupKindInfo::FKF_IsPCRel }, { "fixup_arm_branch", 1, 24, MCFixupKindInfo::FKF_IsPCRel }, - { "fixup_t2_branch", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, + { "fixup_t2_branch", 0, 32, MCFixupKindInfo::FKF_IsPCRel | + MCFixupKindInfo::FKF_IsAligned}, { "fixup_arm_thumb_bl", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, { "fixup_arm_thumb_blx", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, { "fixup_arm_thumb_cb", 0, 16, MCFixupKindInfo::FKF_IsPCRel }, |
