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| author | Tim Northover <tnorthover@apple.com> | 2015-07-16 21:30:21 +0000 |
|---|---|---|
| committer | Tim Northover <tnorthover@apple.com> | 2015-07-16 21:30:21 +0000 |
| commit | ca0ffc356193e319d07d1f5db49db4cc61f45b59 (patch) | |
| tree | 47feaa00a3ed8ec7f41414d296e8f26aee60127a /llvm/lib/Target | |
| parent | 9e694e590cdbd751e026833a042e871b66f192cf (diff) | |
| download | bcm5719-llvm-ca0ffc356193e319d07d1f5db49db4cc61f45b59.tar.gz bcm5719-llvm-ca0ffc356193e319d07d1f5db49db4cc61f45b59.zip | |
AArch64: make inexact signalling on round Darwin-specific
C11 leaves the choice on whether round-to-integer operations set the inexact
flag implementation-defined. Darwin does expect it to be set, but this seems to
be against the intent of the IEEE document and slower to implement anyway. So
it should be opt-in.
llvm-svn: 242446
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp index 772e894f4f0..cf33782365b 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp @@ -2062,7 +2062,7 @@ SDNode *AArch64DAGToDAGISel::SelectLIBM(SDNode *N) { SmallVector<SDValue, 2> Ops; Ops.push_back(In); - if (!TM.Options.UnsafeFPMath) { + if (Subtarget->isTargetDarwin() && !TM.Options.UnsafeFPMath) { SDNode *FRINTX = CurDAG->getMachineNode(FRINTXOpc, dl, VT, MVT::Glue, In); Ops.push_back(SDValue(FRINTX, 1)); } |
