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| author | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2013-05-20 00:53:25 +0000 |
|---|---|---|
| committer | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2013-05-20 00:53:25 +0000 |
| commit | c7bc5fbc5c3d60b347e6eb9d85b85ee656db5c69 (patch) | |
| tree | 01b072cdba0dee9e4f9ae01844d416ccd4cd707f /llvm/lib/Target | |
| parent | 751e9b84077dd3b5cf6f5d5812f2054071a5179c (diff) | |
| download | bcm5719-llvm-c7bc5fbc5c3d60b347e6eb9d85b85ee656db5c69.tar.gz bcm5719-llvm-c7bc5fbc5c3d60b347e6eb9d85b85ee656db5c69.zip | |
Implement spill and fill of I64Regs.
llvm-svn: 182228
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/Sparc/SparcInstrInfo.cpp | 11 |
1 files changed, 9 insertions, 2 deletions
diff --git a/llvm/lib/Target/Sparc/SparcInstrInfo.cpp b/llvm/lib/Target/Sparc/SparcInstrInfo.cpp index 39d7329f266..546292ce646 100644 --- a/llvm/lib/Target/Sparc/SparcInstrInfo.cpp +++ b/llvm/lib/Target/Sparc/SparcInstrInfo.cpp @@ -40,6 +40,7 @@ SparcInstrInfo::SparcInstrInfo(SparcSubtarget &ST) unsigned SparcInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const { if (MI->getOpcode() == SP::LDri || + MI->getOpcode() == SP::LDXri || MI->getOpcode() == SP::LDFri || MI->getOpcode() == SP::LDDFri) { if (MI->getOperand(1).isFI() && MI->getOperand(2).isImm() && @@ -59,6 +60,7 @@ unsigned SparcInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, unsigned SparcInstrInfo::isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const { if (MI->getOpcode() == SP::STri || + MI->getOpcode() == SP::STXri || MI->getOpcode() == SP::STFri || MI->getOpcode() == SP::STDFri) { if (MI->getOperand(0).isFI() && MI->getOperand(1).isImm() && @@ -303,7 +305,10 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, if (I != MBB.end()) DL = I->getDebugLoc(); // On the order of operands here: think "[FrameIdx + 0] = SrcReg". - if (RC == &SP::IntRegsRegClass) + if (RC == &SP::I64RegsRegClass) + BuildMI(MBB, I, DL, get(SP::STXri)).addFrameIndex(FI).addImm(0) + .addReg(SrcReg, getKillRegState(isKill)); + else if (RC == &SP::IntRegsRegClass) BuildMI(MBB, I, DL, get(SP::STri)).addFrameIndex(FI).addImm(0) .addReg(SrcReg, getKillRegState(isKill)); else if (RC == &SP::FPRegsRegClass) @@ -324,7 +329,9 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL; if (I != MBB.end()) DL = I->getDebugLoc(); - if (RC == &SP::IntRegsRegClass) + if (RC == &SP::I64RegsRegClass) + BuildMI(MBB, I, DL, get(SP::LDXri), DestReg).addFrameIndex(FI).addImm(0); + else if (RC == &SP::IntRegsRegClass) BuildMI(MBB, I, DL, get(SP::LDri), DestReg).addFrameIndex(FI).addImm(0); else if (RC == &SP::FPRegsRegClass) BuildMI(MBB, I, DL, get(SP::LDFri), DestReg).addFrameIndex(FI).addImm(0); |
