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| author | Igor Breger <igor.breger@intel.com> | 2016-02-24 08:15:20 +0000 |
|---|---|---|
| committer | Igor Breger <igor.breger@intel.com> | 2016-02-24 08:15:20 +0000 |
| commit | c7ba5699c5a9e908c05a2a94f56852300095a280 (patch) | |
| tree | 4634f6aea1ef12c8859cf4ecc0ec42deed01de0b /llvm/lib/Target | |
| parent | 2c56f33dbf6d56f61ecdff2cc75a2c1a53f16584 (diff) | |
| download | bcm5719-llvm-c7ba5699c5a9e908c05a2a94f56852300095a280.tar.gz bcm5719-llvm-c7ba5699c5a9e908c05a2a94f56852300095a280.zip | |
AVX512: Add vpmovzxbw/d/q ,vpmovzxw/d/q ,vpmovzxbdq lowering patterns that support 256bit inputs like AVX patterns ( that are disable in case HasVLX , see SS41I_pmovx_avx2_patterns).
Differential Revision: http://reviews.llvm.org/D17504
llvm-svn: 261724
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrAVX512.td | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/llvm/lib/Target/X86/X86InstrAVX512.td b/llvm/lib/Target/X86/X86InstrAVX512.td index b3b455a02dc..12e8887b629 100644 --- a/llvm/lib/Target/X86/X86InstrAVX512.td +++ b/llvm/lib/Target/X86/X86InstrAVX512.td @@ -6351,6 +6351,14 @@ multiclass avx512_extend_common<bits<8> opc, string OpcodeStr, } } +// support full register inputs (like SSE paterns) +multiclass avx512_extend_lowering<SDNode OpNode, X86VectorVTInfo To, + X86VectorVTInfo From, SubRegIndex SubRegIdx> { + def : Pat<(To.VT (OpNode (From.VT From.RC:$src))), + (!cast<Instruction>(NAME#To.ZSuffix#"rr") + (EXTRACT_SUBREG From.RC:$src, SubRegIdx))>; +} + multiclass avx512_extend_BW<bits<8> opc, string OpcodeStr, SDNode OpNode, string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi8")> { let Predicates = [HasVLX, HasBWI] in { @@ -6360,6 +6368,7 @@ multiclass avx512_extend_BW<bits<8> opc, string OpcodeStr, SDNode OpNode, defm Z256: avx512_extend_common<opc, OpcodeStr, v16i16x_info, v16i8x_info, i128mem, LdFrag, OpNode>, + avx512_extend_lowering<OpNode, v16i16x_info, v32i8x_info, sub_xmm>, EVEX_CD8<8, CD8VH>, T8PD, EVEX_V256; } let Predicates = [HasBWI] in { @@ -6378,6 +6387,7 @@ multiclass avx512_extend_BD<bits<8> opc, string OpcodeStr, SDNode OpNode, defm Z256: avx512_extend_common<opc, OpcodeStr, v8i32x_info, v16i8x_info, i64mem, LdFrag, OpNode>, + avx512_extend_lowering<OpNode, v8i32x_info, v32i8x_info, sub_xmm>, EVEX_CD8<8, CD8VQ>, T8PD, EVEX_V256; } let Predicates = [HasAVX512] in { @@ -6396,6 +6406,7 @@ multiclass avx512_extend_BQ<bits<8> opc, string OpcodeStr, SDNode OpNode, defm Z256: avx512_extend_common<opc, OpcodeStr, v4i64x_info, v16i8x_info, i32mem, LdFrag, OpNode>, + avx512_extend_lowering<OpNode, v4i64x_info, v32i8x_info, sub_xmm>, EVEX_CD8<8, CD8VO>, T8PD, EVEX_V256; } let Predicates = [HasAVX512] in { @@ -6414,6 +6425,7 @@ multiclass avx512_extend_WD<bits<8> opc, string OpcodeStr, SDNode OpNode, defm Z256: avx512_extend_common<opc, OpcodeStr, v8i32x_info, v8i16x_info, i128mem, LdFrag, OpNode>, + avx512_extend_lowering<OpNode, v8i32x_info, v16i16x_info, sub_xmm>, EVEX_CD8<16, CD8VH>, T8PD, EVEX_V256; } let Predicates = [HasAVX512] in { @@ -6432,6 +6444,7 @@ multiclass avx512_extend_WQ<bits<8> opc, string OpcodeStr, SDNode OpNode, defm Z256: avx512_extend_common<opc, OpcodeStr, v4i64x_info, v8i16x_info, i64mem, LdFrag, OpNode>, + avx512_extend_lowering<OpNode, v4i64x_info, v16i16x_info, sub_xmm>, EVEX_CD8<16, CD8VQ>, T8PD, EVEX_V256; } let Predicates = [HasAVX512] in { @@ -6451,6 +6464,7 @@ multiclass avx512_extend_DQ<bits<8> opc, string OpcodeStr, SDNode OpNode, defm Z256: avx512_extend_common<opc, OpcodeStr, v4i64x_info, v4i32x_info, i128mem, LdFrag, OpNode>, + avx512_extend_lowering<OpNode, v4i64x_info, v8i32x_info, sub_xmm>, EVEX_CD8<32, CD8VH>, T8PD, EVEX_V256; } let Predicates = [HasAVX512] in { |
