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| author | Tom Stellard <tstellar@redhat.com> | 2018-04-24 20:51:28 +0000 |
|---|---|---|
| committer | Tom Stellard <tstellar@redhat.com> | 2018-04-24 20:51:28 +0000 |
| commit | c7709e1c29d2fce5c4fc33f06c21899b24e2a618 (patch) | |
| tree | 9bd3da8ff255da6a34fae1e85208a3f83b6037c8 /llvm/lib/Target | |
| parent | a4e557f90812f1d6ffe347ef368c127f077ac5a3 (diff) | |
| download | bcm5719-llvm-c7709e1c29d2fce5c4fc33f06c21899b24e2a618.tar.gz bcm5719-llvm-c7709e1c29d2fce5c4fc33f06c21899b24e2a618.zip | |
AMDGPU/GlobalISel: Add support for amdgpu_ps calling convention
Reviewers: arsenm
Reviewed By: arsenm
Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D45837
llvm-svn: 330767
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp | 63 |
1 files changed, 49 insertions, 14 deletions
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp index 58e8b687eee..9cb647cae85 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp @@ -139,40 +139,75 @@ bool AMDGPUCallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder, unsigned NumArgs = F.arg_size(); Function::const_arg_iterator CurOrigArg = F.arg_begin(); const AMDGPUTargetLowering &TLI = *getTLI<AMDGPUTargetLowering>(); + unsigned PSInputNum = 0; + BitVector Skipped(NumArgs); for (unsigned i = 0; i != NumArgs; ++i, ++CurOrigArg) { EVT ValEVT = TLI.getValueType(DL, CurOrigArg->getType()); // We can only hanlde simple value types at the moment. - if (!ValEVT.isSimple()) - return false; - MVT ValVT = ValEVT.getSimpleVT(); ISD::ArgFlagsTy Flags; ArgInfo OrigArg{VRegs[i], CurOrigArg->getType()}; setArgFlags(OrigArg, i + 1, DL, F); Flags.setOrigAlign(DL.getABITypeAlignment(CurOrigArg->getType())); + + if (F.getCallingConv() == CallingConv::AMDGPU_PS && + !OrigArg.Flags.isInReg() && !OrigArg.Flags.isByVal() && + PSInputNum <= 15) { + if (CurOrigArg->use_empty() && !Info->isPSInputAllocated(PSInputNum)) { + Skipped.set(i); + ++PSInputNum; + continue; + } + + Info->markPSInputAllocated(PSInputNum); + if (!CurOrigArg->use_empty()) + Info->markPSInputEnabled(PSInputNum); + + ++PSInputNum; + } + CCAssignFn *AssignFn = CCAssignFnForCall(F.getCallingConv(), /*IsVarArg=*/false); - bool Res = - AssignFn(i, ValVT, ValVT, CCValAssign::Full, OrigArg.Flags, CCInfo); - // Fail if we don't know how to handle this type. - if (Res) - return false; + if (ValEVT.isVector()) { + EVT ElemVT = ValEVT.getVectorElementType(); + if (!ValEVT.isSimple()) + return false; + MVT ValVT = ElemVT.getSimpleVT(); + bool Res = AssignFn(i, ValVT, ValVT, CCValAssign::Full, + OrigArg.Flags, CCInfo); + if (!Res) + return false; + } else { + MVT ValVT = ValEVT.getSimpleVT(); + if (!ValEVT.isSimple()) + return false; + bool Res = + AssignFn(i, ValVT, ValVT, CCValAssign::Full, OrigArg.Flags, CCInfo); + + // Fail if we don't know how to handle this type. + if (Res) + return false; + } } Function::const_arg_iterator Arg = F.arg_begin(); - if (F.getCallingConv() == CallingConv::AMDGPU_VS) { - for (unsigned i = 0; i != NumArgs; ++i, ++Arg) { - CCValAssign &VA = ArgLocs[i]; - MRI.addLiveIn(VA.getLocReg(), VRegs[i]); + if (F.getCallingConv() == CallingConv::AMDGPU_VS || + F.getCallingConv() == CallingConv::AMDGPU_PS) { + for (unsigned i = 0, OrigArgIdx = 0; + OrigArgIdx != NumArgs && i != ArgLocs.size(); ++Arg, ++OrigArgIdx) { + if (Skipped.test(OrigArgIdx)) + continue; + CCValAssign &VA = ArgLocs[i++]; + MRI.addLiveIn(VA.getLocReg(), VRegs[OrigArgIdx]); MIRBuilder.getMBB().addLiveIn(VA.getLocReg()); - MIRBuilder.buildCopy(VRegs[i], VA.getLocReg()); + MIRBuilder.buildCopy(VRegs[OrigArgIdx], VA.getLocReg()); } return true; } - for (unsigned i = 0; i != NumArgs; ++i, ++Arg) { + for (unsigned i = 0; i != ArgLocs.size(); ++i, ++Arg) { // FIXME: We should be getting DebugInfo from the arguments some how. CCValAssign &VA = ArgLocs[i]; lowerParameter(MIRBuilder, Arg->getType(), |

