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authorCameron McInally <cameron.mcinally@nyu.edu>2013-11-26 00:20:43 +0000
committerCameron McInally <cameron.mcinally@nyu.edu>2013-11-26 00:20:43 +0000
commitc592e5251c1f118a8749ead970a13600c3a68f41 (patch)
treeafea8c2abb33da7e6114b910f046cb8fd4b9b034 /llvm/lib/Target
parent9d861bed9be4288233c96ba4dcd6666fdbbc5adf (diff)
downloadbcm5719-llvm-c592e5251c1f118a8749ead970a13600c3a68f41.tar.gz
bcm5719-llvm-c592e5251c1f118a8749ead970a13600c3a68f41.zip
Add an intrinsic for the SSE2 PAUSE instruction.
llvm-svn: 195697
Diffstat (limited to 'llvm/lib/Target')
-rw-r--r--llvm/lib/Target/X86/X86InstrSSE.td4
1 files changed, 3 insertions, 1 deletions
diff --git a/llvm/lib/Target/X86/X86InstrSSE.td b/llvm/lib/Target/X86/X86InstrSSE.td
index a5debc02569..8c0076dfd40 100644
--- a/llvm/lib/Target/X86/X86InstrSSE.td
+++ b/llvm/lib/Target/X86/X86InstrSSE.td
@@ -3499,7 +3499,9 @@ def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
// Pause. This "instruction" is encoded as "rep; nop", so even though it
// was introduced with SSE2, it's backward compatible.
-def PAUSE : I<0x90, RawFrm, (outs), (ins), "pause", [], IIC_SSE_PAUSE>, REP;
+def PAUSE : I<0x90, RawFrm, (outs), (ins),
+ "pause", [(int_x86_sse2_pause)], IIC_SSE_PAUSE>,
+ REP, Requires<[HasSSE2]>;
// Load, store, and memory fence
def SFENCE : I<0xAE, MRM_F8, (outs), (ins),
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