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| author | Balaram Makam <bmakam@codeaurora.org> | 2017-04-11 22:14:10 +0000 |
|---|---|---|
| committer | Balaram Makam <bmakam@codeaurora.org> | 2017-04-11 22:14:10 +0000 |
| commit | c53c44cec4c2be9823e34a5d9b3d6079b435ae57 (patch) | |
| tree | c2e0f26420f194b57e938159ddfffcc430e6dce4 /llvm/lib/Target | |
| parent | bb352493085f93f538b505f0290c9afcdcf5d044 (diff) | |
| download | bcm5719-llvm-c53c44cec4c2be9823e34a5d9b3d6079b435ae57.tar.gz bcm5719-llvm-c53c44cec4c2be9823e34a5d9b3d6079b435ae57.zip | |
[AArch64] Fix scheduling info for INS(vector, general) instruction.
llvm-svn: 299994
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64SchedFalkorDetails.td | 2 | ||||
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64SchedFalkorWriteRes.td | 5 |
2 files changed, 6 insertions, 1 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64SchedFalkorDetails.td b/llvm/lib/Target/AArch64/AArch64SchedFalkorDetails.td index 57b24dc40b4..6bce4ef6b65 100644 --- a/llvm/lib/Target/AArch64/AArch64SchedFalkorDetails.td +++ b/llvm/lib/Target/AArch64/AArch64SchedFalkorDetails.td @@ -292,8 +292,8 @@ def : InstRW<[FalkorWr_1VXVY_5cyc], (instrs FRECPS32, FRSQRTS32, FRECPSv2f32, def : InstRW<[FalkorWr_1VXVY_6cyc], (instrs FRECPS64, FRSQRTS64)>; +def : InstRW<[FalkorWr_1GTOV_1VXVY_2cyc],(instregex "^INSv(i32|i64)(gpr|lane)$")>; def : InstRW<[FalkorWr_2GTOV_1cyc], (instregex "^DUP(v4i32|v2i64)(gpr|lane)$")>; -def : InstRW<[FalkorWr_2GTOV_1cyc], (instregex "^INSv(i32|i64)(gpr|lane)$")>; def : InstRW<[FalkorWr_2VXVY_1cyc], (instrs EXTv16i8)>; def : InstRW<[FalkorWr_2VXVY_1cyc], (instregex "(MOVI|MVNI)(v2d_ns|v16b_ns|v4i32|v8i16|v4s_msl)$")>; def : InstRW<[FalkorWr_2VXVY_1cyc], (instrs NOTv16i8)>; diff --git a/llvm/lib/Target/AArch64/AArch64SchedFalkorWriteRes.td b/llvm/lib/Target/AArch64/AArch64SchedFalkorWriteRes.td index 93f930761d7..9cdb4be4246 100644 --- a/llvm/lib/Target/AArch64/AArch64SchedFalkorWriteRes.td +++ b/llvm/lib/Target/AArch64/AArch64SchedFalkorWriteRes.td @@ -118,6 +118,11 @@ def FalkorWr_1VX_1VY_10cyc : SchedWriteRes<[FalkorUnitVX, FalkorUnitVY]> { let NumMicroOps = 2; } +def FalkorWr_1GTOV_1VXVY_2cyc : SchedWriteRes<[FalkorUnitGTOV, FalkorUnitVXVY]> { + let Latency = 2; + let NumMicroOps = 2; +} + def FalkorWr_2GTOV_1cyc : SchedWriteRes<[FalkorUnitGTOV, FalkorUnitGTOV]> { let Latency = 1; let NumMicroOps = 2; |
