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| author | Geoff Berry <gberry@codeaurora.org> | 2016-04-15 15:16:19 +0000 |
|---|---|---|
| committer | Geoff Berry <gberry@codeaurora.org> | 2016-04-15 15:16:19 +0000 |
| commit | c376406669d4051985fdea1a7fc9f67e651baf49 (patch) | |
| tree | b22a8234f566602288aa3a86c15c3833e34981ae /llvm/lib/Target | |
| parent | 1f51c334ca0e41424d4e821c9a63896c5cfe68ab (diff) | |
| download | bcm5719-llvm-c376406669d4051985fdea1a7fc9f67e651baf49.tar.gz bcm5719-llvm-c376406669d4051985fdea1a7fc9f67e651baf49.zip | |
[AArch64] Add MMOs to callee-save load/store instructions.
Summary:
Without MMOs, the callee-save load/store instructions were treated as
volatile by the MI post-RA scheduler and AArch64LoadStoreOptimizer.
Reviewers: t.p.northover, mcrosier
Subscribers: aemerson, rengolin, mcrosier, llvm-commits
Differential Revision: http://reviews.llvm.org/D17661
llvm-svn: 266439
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64FrameLowering.cpp | 17 |
1 files changed, 15 insertions, 2 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp b/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp index 57e320ab267..f567b624beb 100644 --- a/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp @@ -871,6 +871,9 @@ bool AArch64FrameLowering::spillCalleeSavedRegisters( .addReg(AArch64::SP) .addImm(Offset) // [sp, #offset * 8], where factor * 8 is implicit .setMIFlag(MachineInstr::FrameSetup); + MIB.addMemOperand(MF.getMachineMemOperand( + MachinePointerInfo::getFixedStack(MF, RPI.FrameIdx + 1), + MachineMemOperand::MOStore, 8, 8)); } else { MBB.addLiveIn(Reg1); MIB.addReg(Reg1, getPrologueDeath(MF, Reg1)) @@ -878,6 +881,9 @@ bool AArch64FrameLowering::spillCalleeSavedRegisters( .addImm(BumpSP ? Offset * 8 : Offset) // pre-inc version is unscaled .setMIFlag(MachineInstr::FrameSetup); } + MIB.addMemOperand(MF.getMachineMemOperand( + MachinePointerInfo::getFixedStack(MF, RPI.FrameIdx), + MachineMemOperand::MOStore, 8, 8)); } return true; } @@ -935,18 +941,25 @@ bool AArch64FrameLowering::restoreCalleeSavedRegisters( if (BumpSP) MIB.addReg(AArch64::SP, RegState::Define); - if (RPI.isPaired()) + if (RPI.isPaired()) { MIB.addReg(Reg2, getDefRegState(true)) .addReg(Reg1, getDefRegState(true)) .addReg(AArch64::SP) .addImm(Offset) // [sp], #offset * 8 or [sp, #offset * 8] // where the factor * 8 is implicit .setMIFlag(MachineInstr::FrameDestroy); - else + MIB.addMemOperand(MF.getMachineMemOperand( + MachinePointerInfo::getFixedStack(MF, RPI.FrameIdx + 1), + MachineMemOperand::MOLoad, 8, 8)); + } else { MIB.addReg(Reg1, getDefRegState(true)) .addReg(AArch64::SP) .addImm(BumpSP ? Offset * 8 : Offset) // post-dec version is unscaled .setMIFlag(MachineInstr::FrameDestroy); + } + MIB.addMemOperand(MF.getMachineMemOperand( + MachinePointerInfo::getFixedStack(MF, RPI.FrameIdx), + MachineMemOperand::MOLoad, 8, 8)); } return true; } |
