diff options
| author | Richard Barton <richard.barton@arm.com> | 2013-11-22 11:53:16 +0000 |
|---|---|---|
| committer | Richard Barton <richard.barton@arm.com> | 2013-11-22 11:53:16 +0000 |
| commit | c31078cded9e5c8ecc8a4b24c7292a5d0d447268 (patch) | |
| tree | 05d0e279107aa3b28aea3873cd78d51072b6aad3 /llvm/lib/Target | |
| parent | bf950c0f6fecd3e1c9c9ea0e2f80fc3b41ac512b (diff) | |
| download | bcm5719-llvm-c31078cded9e5c8ecc8a4b24c7292a5d0d447268.tar.gz bcm5719-llvm-c31078cded9e5c8ecc8a4b24c7292a5d0d447268.zip | |
Add support for Cortex-A12.
Patch by Oliver Stannard!
llvm-svn: 195448
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/ARM/ARM.td | 17 | ||||
| -rw-r--r-- | llvm/lib/Target/ARM/ARMSubtarget.h | 4 |
2 files changed, 19 insertions, 2 deletions
diff --git a/llvm/lib/Target/ARM/ARM.td b/llvm/lib/Target/ARM/ARM.td index daa3793c195..f63064eeb0b 100644 --- a/llvm/lib/Target/ARM/ARM.td +++ b/llvm/lib/Target/ARM/ARM.td @@ -205,6 +205,15 @@ def ProcSwift : SubtargetFeature<"swift", "ARMProcFamily", "Swift", FeatureHWDivARM, FeatureAvoidPartialCPSR, FeatureAvoidMOVsShOp, FeatureHasSlowFPVMLx, FeatureTrustZone]>; +def ProcA12 : SubtargetFeature<"a12", "ARMProcFamily", "CortexA12", + "Cortex-A12 ARM processors", + [FeatureVMLxForwarding, + FeatureT2XtPk, FeatureVFP4, + FeatureHWDiv, FeatureHWDivARM, + FeatureAvoidPartialCPSR, + FeatureVirtualization, + FeatureTrustZone]>; + // FIXME: It has not been determined if A15 has these features. def ProcA15 : SubtargetFeature<"a15", "ARMProcFamily", "CortexA15", @@ -319,11 +328,19 @@ def : ProcessorModel<"cortex-a9-mp", CortexA9Model, [ProcA9, HasV7Ops, FeatureNEON, FeatureDB, FeatureDSPThumb2, FeatureMP, FeatureHasRAS, FeatureAClass]>; + +// FIXME: A12 has currently the same Schedule model as A9 +def : ProcessorModel<"cortex-a12", CortexA9Model, + [ProcA12, HasV7Ops, FeatureNEON, FeatureDB, + FeatureDSPThumb2, FeatureMP, + FeatureHasRAS, FeatureAClass]>; + // FIXME: A15 has currently the same ProcessorModel as A9. def : ProcessorModel<"cortex-a15", CortexA9Model, [ProcA15, HasV7Ops, FeatureNEON, FeatureDB, FeatureDSPThumb2, FeatureHasRAS, FeatureAClass]>; + // FIXME: R5 has currently the same ProcessorModel as A8. def : ProcessorModel<"cortex-r5", CortexA8Model, [ProcR5, HasV7Ops, FeatureDB, diff --git a/llvm/lib/Target/ARM/ARMSubtarget.h b/llvm/lib/Target/ARM/ARMSubtarget.h index 5fc9f8f460b..ca5ba8541f7 100644 --- a/llvm/lib/Target/ARM/ARMSubtarget.h +++ b/llvm/lib/Target/ARM/ARMSubtarget.h @@ -31,8 +31,8 @@ class TargetOptions; class ARMSubtarget : public ARMGenSubtargetInfo { protected: enum ARMProcFamilyEnum { - Others, CortexA5, CortexA7, CortexA8, CortexA9, CortexA15, CortexR5, - Swift, CortexA53, CortexA57 + Others, CortexA5, CortexA7, CortexA8, CortexA9, CortexA12, CortexA15, + CortexR5, Swift, CortexA53, CortexA57 }; enum ARMProcClassEnum { None, AClass, RClass, MClass |
