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| author | Sander de Smalen <sander.desmalen@arm.com> | 2018-07-09 09:12:17 +0000 |
|---|---|---|
| committer | Sander de Smalen <sander.desmalen@arm.com> | 2018-07-09 09:12:17 +0000 |
| commit | bd513b42a12c282901e837b75a6116f1d99a2d5c (patch) | |
| tree | 23eb20eec59fd26383039a60721980ce036a730b /llvm/lib/Target | |
| parent | 3703551135449fd051b1cf664c6d6043d9ef77dd (diff) | |
| download | bcm5719-llvm-bd513b42a12c282901e837b75a6116f1d99a2d5c.tar.gz bcm5719-llvm-bd513b42a12c282901e837b75a6116f1d99a2d5c.zip | |
[AArch64][SVE] Asm: Support for UZP and TRN instructions.
This patch adds support for:
UZP1 Concatenate even elements from two vectors
UZP2 Concatenate odd elements from two vectors
TRN1 Interleave even elements from two vectors
TRN2 Interleave odd elements from two vectors
With variants for both data and predicate vectors, e.g.
uzp1 z0.b, z1.b, z2.b
trn2 p0.s, p1.s, p2.s
llvm-svn: 336531
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td index a6067af111a..87617de9fc2 100644 --- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td @@ -536,9 +536,17 @@ let Predicates = [HasSVE] in { defm ZIP1_ZZZ : sve_int_perm_bin_perm_zz<0b000, "zip1">; defm ZIP2_ZZZ : sve_int_perm_bin_perm_zz<0b001, "zip2">; + defm UZP1_ZZZ : sve_int_perm_bin_perm_zz<0b010, "uzp1">; + defm UZP2_ZZZ : sve_int_perm_bin_perm_zz<0b011, "uzp2">; + defm TRN1_ZZZ : sve_int_perm_bin_perm_zz<0b100, "trn1">; + defm TRN2_ZZZ : sve_int_perm_bin_perm_zz<0b101, "trn2">; defm ZIP1_PPP : sve_int_perm_bin_perm_pp<0b000, "zip1">; defm ZIP2_PPP : sve_int_perm_bin_perm_pp<0b001, "zip2">; + defm UZP1_PPP : sve_int_perm_bin_perm_pp<0b010, "uzp1">; + defm UZP2_PPP : sve_int_perm_bin_perm_pp<0b011, "uzp2">; + defm TRN1_PPP : sve_int_perm_bin_perm_pp<0b100, "trn1">; + defm TRN2_PPP : sve_int_perm_bin_perm_pp<0b101, "trn2">; def RDVLI_XI : sve_int_read_vl_a<0b0, 0b11111, "rdvl">; def ADDVL_XXI : sve_int_arith_vl<0b0, "addvl">; |
