Added the target-independent part of TableGen data.

llvm-svn: 6403

1 files changed, 26 insertions, 0 deletions

diff --git a/llvm/lib/Target/Target.td b/llvm/lib/Target/Target.td
new file mode 100644
index 00000000000..da3033c40ad
--- /dev/null
+++ b/llvm/lib/Target/Target.td
@@ -0,0 +1,26 @@
+//===- Sparc.td - Target Description for Sparc V9 Target --------*- C++ -*-===//
+// vim:ft=cpp
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+//  Target-Independent interface
+//===----------------------------------------------------------------------===//
+
+class Register {
+  string Namespace = "";
+  int Size;
+}
+
+class Instruction {
+  string Name;          // The opcode string for this instruction
+  string Namespace = "";
+
+  list<Register> Uses = [];  // Default to using no non-operand registers
+  list<Register> Defs = [];  // Default to modifying no non-operand registers
+
+  // These bits capture information about the high-level semantics of the
+  // instruction.
+  bit isReturn     = 0;      // Is this instruction a return instruction?
+  bit isBranch     = 0;      // Is this instruction a branch instruction?
+  bit isCall       = 0;      // Is this instruction a call instruction?
+}