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| author | Craig Topper <craig.topper@gmail.com> | 2017-01-26 07:17:58 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@gmail.com> | 2017-01-26 07:17:58 +0000 |
| commit | bad53cce26cf4709632d6d3ca7dd9a3f070b710c (patch) | |
| tree | 4c1201fbbbd53b899f13f45c5970df01ede7cec3 /llvm/lib/Target | |
| parent | f0bab7b7395970fbd4ce3600731f932c89d3000b (diff) | |
| download | bcm5719-llvm-bad53cce26cf4709632d6d3ca7dd9a3f070b710c.tar.gz bcm5719-llvm-bad53cce26cf4709632d6d3ca7dd9a3f070b710c.zip | |
[AVX-512] Move the combine that runs combineBitcastForMaskedOp to the last DAG combine phase where I had originally meant to put it.
llvm-svn: 293157
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 79e58ba4b03..7dc37f432db 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -29505,7 +29505,7 @@ static SDValue combineSelect(SDNode *N, SelectionDAG &DAG, // Look for vselects with LHS/RHS being bitcasted from an operation that // can be executed on another type. Push the bitcast to the inputs of // the operation. This exposes opportunities for using masking instructions. - if (N->getOpcode() == ISD::VSELECT && !DCI.isBeforeLegalizeOps() && + if (N->getOpcode() == ISD::VSELECT && DCI.isAfterLegalizeVectorOps() && CondVT.getVectorElementType() == MVT::i1) { if (combineBitcastForMaskedOp(LHS, DAG, DCI)) return SDValue(N, 0); |
