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| author | Justin Bogner <mail@justinbogner.com> | 2016-07-06 19:52:27 +0000 |
|---|---|---|
| committer | Justin Bogner <mail@justinbogner.com> | 2016-07-06 19:52:27 +0000 |
| commit | b3745b6d244e90a6ef2a858e6d87a410e1049727 (patch) | |
| tree | da3caaa71329b3a8682be4d31c90c92e88872099 /llvm/lib/Target | |
| parent | 820ca5404ce9b919ad9be94049298bcec81ce3fa (diff) | |
| download | bcm5719-llvm-b3745b6d244e90a6ef2a858e6d87a410e1049727.tar.gz bcm5719-llvm-b3745b6d244e90a6ef2a858e6d87a410e1049727.zip | |
NVPTX: Make the llvm.nvvm.shfl intrinsics and builtin names consistent
The intrinsics here use nvvm, but the builtins and tablegen variable
names were using ptx. Stick to the modern names here.
llvm-svn: 274662
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/NVPTX/NVPTXIntrinsics.td | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/llvm/lib/Target/NVPTX/NVPTXIntrinsics.td b/llvm/lib/Target/NVPTX/NVPTXIntrinsics.td index ddb569a7421..6f7df39c771 100644 --- a/llvm/lib/Target/NVPTX/NVPTXIntrinsics.td +++ b/llvm/lib/Target/NVPTX/NVPTXIntrinsics.td @@ -96,14 +96,14 @@ multiclass SHFL<NVPTXRegClass regclass, string mode, Intrinsic IntOp> { [(set regclass:$dst, (IntOp regclass:$src, imm:$offset, imm:$mask))]>; } -defm INT_SHFL_DOWN_I32 : SHFL<Int32Regs, "down", int_ptx_shfl_down_i32>; -defm INT_SHFL_DOWN_F32 : SHFL<Float32Regs, "down", int_ptx_shfl_down_f32>; -defm INT_SHFL_UP_I32 : SHFL<Int32Regs, "up", int_ptx_shfl_up_i32>; -defm INT_SHFL_UP_F32 : SHFL<Float32Regs, "up", int_ptx_shfl_up_f32>; -defm INT_SHFL_BFLY_I32 : SHFL<Int32Regs, "bfly", int_ptx_shfl_bfly_i32>; -defm INT_SHFL_BFLY_F32 : SHFL<Float32Regs, "bfly", int_ptx_shfl_bfly_f32>; -defm INT_SHFL_IDX_I32 : SHFL<Int32Regs, "idx", int_ptx_shfl_idx_i32>; -defm INT_SHFL_IDX_F32 : SHFL<Float32Regs, "idx", int_ptx_shfl_idx_f32>; +defm INT_SHFL_DOWN_I32 : SHFL<Int32Regs, "down", int_nvvm_shfl_down_i32>; +defm INT_SHFL_DOWN_F32 : SHFL<Float32Regs, "down", int_nvvm_shfl_down_f32>; +defm INT_SHFL_UP_I32 : SHFL<Int32Regs, "up", int_nvvm_shfl_up_i32>; +defm INT_SHFL_UP_F32 : SHFL<Float32Regs, "up", int_nvvm_shfl_up_f32>; +defm INT_SHFL_BFLY_I32 : SHFL<Int32Regs, "bfly", int_nvvm_shfl_bfly_i32>; +defm INT_SHFL_BFLY_F32 : SHFL<Float32Regs, "bfly", int_nvvm_shfl_bfly_f32>; +defm INT_SHFL_IDX_I32 : SHFL<Int32Regs, "idx", int_nvvm_shfl_idx_i32>; +defm INT_SHFL_IDX_F32 : SHFL<Float32Regs, "idx", int_nvvm_shfl_idx_f32>; } // isConvergent = 1 |
