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| author | Kai Luo <lkail@cn.ibm.com> | 2020-04-01 02:15:25 +0000 |
|---|---|---|
| committer | Tom Stellard <tstellar@redhat.com> | 2020-04-22 14:54:22 -0700 |
| commit | b11ecd196540d87cb7db190d405056984740d2ce (patch) | |
| tree | 20ba8c440d36363f2fccffc7510736a4fffc3ebe /llvm/lib/Target | |
| parent | 66cfbf17a18513de5551d6cdda563a2864d13400 (diff) | |
| download | bcm5719-llvm-b11ecd196540d87cb7db190d405056984740d2ce.tar.gz bcm5719-llvm-b11ecd196540d87cb7db190d405056984740d2ce.zip | |
[PowerPC] Don't generate ST_VSR_SCAL_INT if power8-vector is disabled
Summary:
In https://bugs.llvm.org/show_bug.cgi?id=45297, it fails selecting
instructions for `PPCISD::ST_VSR_SCAL_INT`. The reason it generate the
`PPCISD::ST_VSR_SCAL_INT` with `-power8-vector` in IR is PPC's
combiner checks `hasP8Altivec` rather than `hasP8Vector`. This patch
should resolve PR45297.
Differential Revision: https://reviews.llvm.org/D76773
(cherry picked from commit 8eb40e41f6ec99985a292e342ec303a0bd6f5f41)
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp index 764563c17c2..352a05529bc 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -13591,7 +13591,7 @@ SDValue PPCTargetLowering::combineStoreFPToInt(SDNode *N, (Op1VT == MVT::i32 || Op1VT == MVT::i64 || (Subtarget.hasP9Vector() && (Op1VT == MVT::i16 || Op1VT == MVT::i8))); - if (ResVT == MVT::ppcf128 || !Subtarget.hasP8Altivec() || + if (ResVT == MVT::ppcf128 || !Subtarget.hasP8Vector() || cast<StoreSDNode>(N)->isTruncatingStore() || !ValidTypeForStoreFltAsInt) return SDValue(); |
