Use TRI::has{Sub,Super}ClassEq() where possible.

No functional change.

llvm-svn: 132455

4 files changed, 5 insertions, 6 deletions

diff --git a/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp b/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp
index 33cefb6e79b..6bf565068e4 100644
--- a/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp
+++ b/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp
@@ -49,7 +49,7 @@ Thumb1RegisterInfo::Thumb1RegisterInfo(const ARMBaseInstrInfo &tii,
 const TargetRegisterClass*
 Thumb1RegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC)
                                                                          const {
-  if (RC == ARM::tGPRRegisterClass || RC->hasSuperClass(ARM::tGPRRegisterClass))
+  if (ARM::tGPRRegClass.hasSubClassEq(RC))
     return ARM::tGPRRegisterClass;
   return ARMBaseRegisterInfo::getLargestLegalSuperClass(RC);
 }
diff --git a/llvm/lib/Target/Blackfin/BlackfinISelDAGToDAG.cpp b/llvm/lib/Target/Blackfin/BlackfinISelDAGToDAG.cpp
index 9df2aeeecbc..42659aed5d7 100644
--- a/llvm/lib/Target/Blackfin/BlackfinISelDAGToDAG.cpp
+++ b/llvm/lib/Target/Blackfin/BlackfinISelDAGToDAG.cpp
@@ -117,11 +117,11 @@ bool BlackfinDAGToDAGISel::SelectADDRspii(SDValue Addr,
 }
 
 static inline bool isCC(const TargetRegisterClass *RC) {
-  return RC == &BF::AnyCCRegClass || BF::AnyCCRegClass.hasSubClass(RC);
+  return BF::AnyCCRegClass.hasSubClassEq(RC);
 }
 
 static inline bool isDCC(const TargetRegisterClass *RC) {
-  return RC == &BF::DRegClass || BF::DRegClass.hasSubClass(RC) || isCC(RC);
+  return BF::DRegClass.hasSubClassEq(RC) || isCC(RC);
 }
 
 static void UpdateNodeOperand(SelectionDAG &DAG,
diff --git a/llvm/lib/Target/Blackfin/BlackfinInstrInfo.cpp b/llvm/lib/Target/Blackfin/BlackfinInstrInfo.cpp
index e50d57a31b6..598cf2a68c6 100644
--- a/llvm/lib/Target/Blackfin/BlackfinInstrInfo.cpp
+++ b/llvm/lib/Target/Blackfin/BlackfinInstrInfo.cpp
@@ -160,7 +160,7 @@ static bool inClass(const TargetRegisterClass &Test,
   if (TargetRegisterInfo::isPhysicalRegister(Reg))
     return Test.contains(Reg);
   else
-    return &Test==RC || Test.hasSubClass(RC);
+    return Test.hasSubClassEq(RC);
 }
 
 void
diff --git a/llvm/lib/Target/X86/X86RegisterInfo.cpp b/llvm/lib/Target/X86/X86RegisterInfo.cpp
index 68cc2cf3bf8..6f67101e7ef 100644
--- a/llvm/lib/Target/X86/X86RegisterInfo.cpp
+++ b/llvm/lib/Target/X86/X86RegisterInfo.cpp
@@ -261,8 +261,7 @@ X86RegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
     }
     break;
   case X86::sub_8bit_hi:
-    if (B == &X86::GR8_ABCD_HRegClass ||
-        B->hasSubClass(&X86::GR8_ABCD_HRegClass))
+    if (B->hasSubClassEq(&X86::GR8_ABCD_HRegClass))
       switch (A->getSize()) {
         case 2: return getCommonSubClass(A, &X86::GR16_ABCDRegClass);
         case 4: return getCommonSubClass(A, &X86::GR32_ABCDRegClass);