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| author | Richard Osborne <richard@xmos.com> | 2011-09-23 16:28:10 +0000 |
|---|---|---|
| committer | Richard Osborne <richard@xmos.com> | 2011-09-23 16:28:10 +0000 |
| commit | ae191ef63b892f6597a2de48c45e68270ac2fedc (patch) | |
| tree | 62a4c288e0a6bb10841e4589290f1beb8a4ddc7c /llvm/lib/Target | |
| parent | dbe8111948d372a6f7445e86a0ac985717fbe1bc (diff) | |
| download | bcm5719-llvm-ae191ef63b892f6597a2de48c45e68270ac2fedc.tar.gz bcm5719-llvm-ae191ef63b892f6597a2de48c45e68270ac2fedc.zip | |
Fix 80 column violations.
Original patch by Liu.
llvm-svn: 140385
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/XCore/XCoreFrameLowering.cpp | 3 | ||||
| -rw-r--r-- | llvm/lib/Target/XCore/XCoreISelLowering.cpp | 3 | ||||
| -rw-r--r-- | llvm/lib/Target/XCore/XCoreInstrInfo.td | 18 |
3 files changed, 16 insertions, 8 deletions
diff --git a/llvm/lib/Target/XCore/XCoreFrameLowering.cpp b/llvm/lib/Target/XCore/XCoreFrameLowering.cpp index e4cbeb9cda8..7f8b169819a 100644 --- a/llvm/lib/Target/XCore/XCoreFrameLowering.cpp +++ b/llvm/lib/Target/XCore/XCoreFrameLowering.cpp @@ -100,7 +100,8 @@ void XCoreFrameLowering::emitPrologue(MachineFunction &MF) const { DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc(); bool FP = hasFP(MF); - bool Nested = MF.getFunction()->getAttributes().hasAttrSomewhere(Attribute::Nest); + bool Nested = MF.getFunction()-> + getAttributes().hasAttrSomewhere(Attribute::Nest); if (Nested) { loadFromStack(MBB, MBBI, XCore::R11, 0, dl, TII); diff --git a/llvm/lib/Target/XCore/XCoreISelLowering.cpp b/llvm/lib/Target/XCore/XCoreISelLowering.cpp index 42dfdb73554..2afe0e35afb 100644 --- a/llvm/lib/Target/XCore/XCoreISelLowering.cpp +++ b/llvm/lib/Target/XCore/XCoreISelLowering.cpp @@ -1415,7 +1415,8 @@ SDValue XCoreTargetLowering::PerformDAGCombine(SDNode *N, // operands are constant canonicalize smallest to RHS. if ((N0C && !N1C) || (N0C && N1C && N0C->getZExtValue() < N1C->getZExtValue())) - return DAG.getNode(XCoreISD::LMUL, dl, DAG.getVTList(VT, VT), N1, N0, N2, N3); + return DAG.getNode(XCoreISD::LMUL, dl, DAG.getVTList(VT, VT), + N1, N0, N2, N3); // lmul(x, 0, a, b) if (N1C && N1C->isNullValue()) { diff --git a/llvm/lib/Target/XCore/XCoreInstrInfo.td b/llvm/lib/Target/XCore/XCoreInstrInfo.td index c0cd37c5b8b..4d2e93bc7a0 100644 --- a/llvm/lib/Target/XCore/XCoreInstrInfo.td +++ b/llvm/lib/Target/XCore/XCoreInstrInfo.td @@ -766,19 +766,23 @@ def NEG : _F2R<(outs GRRegs:$dst), (ins GRRegs:$b), let Constraints = "$src1 = $dst" in { def SEXT_rus : _FRUS<(outs GRRegs:$dst), (ins GRRegs:$src1, i32imm:$src2), "sext $dst, $src2", - [(set GRRegs:$dst, (int_xcore_sext GRRegs:$src1, immBitp:$src2))]>; + [(set GRRegs:$dst, (int_xcore_sext GRRegs:$src1, + immBitp:$src2))]>; def SEXT_2r : _FRUS<(outs GRRegs:$dst), (ins GRRegs:$src1, GRRegs:$src2), "sext $dst, $src2", - [(set GRRegs:$dst, (int_xcore_sext GRRegs:$src1, GRRegs:$src2))]>; + [(set GRRegs:$dst, (int_xcore_sext GRRegs:$src1, + GRRegs:$src2))]>; def ZEXT_rus : _FRUS<(outs GRRegs:$dst), (ins GRRegs:$src1, i32imm:$src2), "zext $dst, $src2", - [(set GRRegs:$dst, (int_xcore_zext GRRegs:$src1, immBitp:$src2))]>; + [(set GRRegs:$dst, (int_xcore_zext GRRegs:$src1, + immBitp:$src2))]>; def ZEXT_2r : _FRUS<(outs GRRegs:$dst), (ins GRRegs:$src1, GRRegs:$src2), "zext $dst, $src2", - [(set GRRegs:$dst, (int_xcore_zext GRRegs:$src1, GRRegs:$src2))]>; + [(set GRRegs:$dst, (int_xcore_zext GRRegs:$src1, + GRRegs:$src2))]>; def ANDNOT_2r : _F2R<(outs GRRegs:$dst), (ins GRRegs:$src1, GRRegs:$src2), "andnot $dst, $src2", @@ -825,7 +829,8 @@ def OUT_2r : _F2R<(outs), (ins GRRegs:$r, GRRegs:$val), let Constraints = "$src = $dst" in def OUTSHR_2r : _F2R<(outs GRRegs:$dst), (ins GRRegs:$r, GRRegs:$src), "outshr res[$r], $src", - [(set GRRegs:$dst, (int_xcore_outshr GRRegs:$r, GRRegs:$src))]>; + [(set GRRegs:$dst, (int_xcore_outshr GRRegs:$r, + GRRegs:$src))]>; def INCT_2r : _F2R<(outs GRRegs:$dst), (ins GRRegs:$r), "inct $dst, res[$r]", @@ -842,7 +847,8 @@ def IN_2r : _F2R<(outs GRRegs:$dst), (ins GRRegs:$r), let Constraints = "$src = $dst" in def INSHR_2r : _F2R<(outs GRRegs:$dst), (ins GRRegs:$r, GRRegs:$src), "inshr $dst, res[$r]", - [(set GRRegs:$dst, (int_xcore_inshr GRRegs:$r, GRRegs:$src))]>; + [(set GRRegs:$dst, (int_xcore_inshr GRRegs:$r, + GRRegs:$src))]>; def CHKCT_2r : _F2R<(outs), (ins GRRegs:$r, GRRegs:$val), "chkct res[$r], $val", |
