Part 1 of 3 patches that completes very long conditional branches

in constant islands for Mips16. We introdcuce JalB16 as a synomnym
for Jal16. It makes it easier to read and is also necessary because
Jal16 is a call instruction but JalB16 is being used as a branch.
Various parts of LLVM will not work properly even in this late stage of
the backend if we use what was declared as a call instruction to function
as a branch. For one, basic block labels may not get emitted in some
situations. 

llvm-svn: 195968

2 files changed, 44 insertions, 16 deletions

diff --git a/llvm/lib/Target/Mips/Mips16InstrInfo.td b/llvm/lib/Target/Mips/Mips16InstrInfo.td
index 7f2d925f4f0..d9e4a7b62d0 100644
--- a/llvm/lib/Target/Mips/Mips16InstrInfo.td
+++ b/llvm/lib/Target/Mips/Mips16InstrInfo.td
@@ -120,6 +120,15 @@ class FJAL16_ins<bits<1> _X, string asmstr,
          itin>  {
   let isCodeGenOnly=1;
 }
+
+class FJALB16_ins<bits<1> _X, string asmstr,
+                 InstrItinClass itin>:
+  FJAL16<_X, (outs), (ins simm20:$imm),
+         !strconcat(asmstr, "\t$imm\t# branch\n\tnop"),[],
+         itin>  {
+  let isCodeGenOnly=1;
+}
+
 //
 // EXT-I instruction format
 //
@@ -737,6 +746,12 @@ def Jal16 : FJAL16_ins<0b0, "jal", IIAlu> {
   let Defs = [RA];
 }
 
+def JalB16 : FJALB16_ins<0b0, "jal", IIAlu>, branch16 {
+  let hasDelaySlot = 0;  // not true, but we add the nop for now
+  let isBranch=1;
+  let Defs = [RA];
+}
+
 //
 // Format: JR ra MIPS16e
 // Purpose: Jump Register Through Register ra
diff --git a/llvm/lib/Target/Mips/MipsConstantIslandPass.cpp b/llvm/lib/Target/Mips/MipsConstantIslandPass.cpp
index 3c62baeec15..e05fe0abac0 100644
--- a/llvm/lib/Target/Mips/MipsConstantIslandPass.cpp
+++ b/llvm/lib/Target/Mips/MipsConstantIslandPass.cpp
@@ -85,7 +85,7 @@ static unsigned int branchTargetOperand(MachineInstr *MI) {
   case Mips::BteqzX16:
   case Mips::Btnez16:
   case Mips::BtnezX16:
-  case Mips::Jal16:
+  case Mips::JalB16:
     return 0;
   case Mips::BeqzRxImm16:
   case Mips::BeqzRxImmX16:
@@ -96,6 +96,16 @@ static unsigned int branchTargetOperand(MachineInstr *MI) {
   llvm_unreachable("Unknown branch type");
 }
 
+static bool isUnconditionalBranch(unsigned int Opcode) {
+  switch (Opcode) {
+  default: return false;
+  case Mips::Bimm16:
+  case Mips::BimmX16:
+  case Mips::JalB16:
+    return true;
+  }
+}
+
 static unsigned int longformBranchOpcode(unsigned int Opcode) {
   switch (Opcode) {
   case Mips::Bimm16:
@@ -107,8 +117,8 @@ static unsigned int longformBranchOpcode(unsigned int Opcode) {
   case Mips::Btnez16:
   case Mips::BtnezX16:
     return Mips::BtnezX16;
-  case Mips::Jal16:
-    return Mips::Jal16;
+  case Mips::JalB16:
+    return Mips::JalB16;
   case Mips::BeqzRxImm16:
   case Mips::BeqzRxImmX16:
     return Mips::BeqzRxImmX16;
@@ -1561,7 +1571,7 @@ MipsConstantIslands::fixupUnconditionalBr(ImmBranch &Br) {
     //
     DestBB->setAlignment(2);
     Br.MaxDisp = ((1<<24)-1) * 2;
-    MI->setDesc(TII->get(Mips::Jal16));
+    MI->setDesc(TII->get(Mips::JalB16));
   }
   BBInfo[MBB->getNumber()].Size += 2;
   adjustBBOffsetsAfter(MBB);
@@ -1592,17 +1602,14 @@ MipsConstantIslands::fixupConditionalBr(ImmBranch &Br) {
     MI->setDesc(TII->get(LongFormOpcode));
     return true;
   }
-  llvm_unreachable("Fixup of very long conditional branch not working yet.");
 
   // Add an unconditional branch to the destination and invert the branch
   // condition to jump over it:
-  // blt L1
+  // bteqz L1
   // =>
-  // bge L2
+  // bnez L2
   // b   L1
   // L2:
-  unsigned CCReg = 0;  // FIXME
-  unsigned CC=0; //FIXME
 
   // If the branch is at the end of its MBB and that has a fall-through block,
   // direct the updated conditional branch to the fall-through block. Otherwise,
@@ -1611,28 +1618,34 @@ MipsConstantIslands::fixupConditionalBr(ImmBranch &Br) {
   MachineInstr *BMI = &MBB->back();
   bool NeedSplit = (BMI != MI) || !BBHasFallthrough(MBB);
 
+ 
   ++NumCBrFixed;
   if (BMI != MI) {
     if (llvm::next(MachineBasicBlock::iterator(MI)) == prior(MBB->end()) &&
-        BMI->getOpcode() == Br.UncondBr) {
+        isUnconditionalBranch(BMI->getOpcode())) {
       // Last MI in the BB is an unconditional branch. Can we simply invert the
       // condition and swap destinations:
-      // beq L1
+      // beqz L1
       // b   L2
       // =>
-      // bne L2
+      // bnez L2
       // b   L1
-      MachineBasicBlock *NewDest = BMI->getOperand(0).getMBB();
+      unsigned BMITargetOperand = branchTargetOperand(BMI);
+      MachineBasicBlock *NewDest = 
+        BMI->getOperand(BMITargetOperand).getMBB();
       if (isBBInRange(MI, NewDest, Br.MaxDisp)) {
         DEBUG(dbgs() << "  Invert Bcc condition and swap its destination with "
                      << *BMI);
-        BMI->getOperand(0).setMBB(DestBB);
-        MI->getOperand(0).setMBB(NewDest);
+        MI->setDesc(TII->get(TII->getOppositeBranchOpc(Opcode)));
+        BMI->getOperand(BMITargetOperand).setMBB(DestBB);
+        MI->getOperand(TargetOperand).setMBB(NewDest);
         return true;
       }
     }
   }
 
+  llvm_unreachable("unsupported range of unconditional branch");
+
   if (NeedSplit) {
     splitBlockBeforeInstr(MI);
     // No need for the branch to the next block. We're adding an unconditional
@@ -1651,7 +1664,7 @@ MipsConstantIslands::fixupConditionalBr(ImmBranch &Br) {
   // Insert a new conditional branch and a new unconditional branch.
   // Also update the ImmBranch as well as adding a new entry for the new branch.
   BuildMI(MBB, DebugLoc(), TII->get(MI->getOpcode()))
-    .addMBB(NextBB).addImm(CC).addReg(CCReg);
+    .addMBB(NextBB);
   Br.MI = &MBB->back();
   BBInfo[MBB->getNumber()].Size += TII->GetInstSizeInBytes(&MBB->back());
   BuildMI(MBB, DebugLoc(), TII->get(Br.UncondBr)).addMBB(DestBB);