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authorBill Wendling <isanbard@gmail.com>2011-10-17 22:26:23 +0000
committerBill Wendling <isanbard@gmail.com>2011-10-17 22:26:23 +0000
commitaa9047d3f5ee40d752ddc216d8bc1fcf1c0eaa66 (patch)
tree8fd1b1c41717d1c9ced1a2e82c8e2a8437cbeb5d /llvm/lib/Target
parent741cd73aabed61a94642707134eec04b6b299ade (diff)
downloadbcm5719-llvm-aa9047d3f5ee40d752ddc216d8bc1fcf1c0eaa66.tar.gz
bcm5719-llvm-aa9047d3f5ee40d752ddc216d8bc1fcf1c0eaa66.zip
Now Igor, throw the switch...give my creation life!
Use the custom inserter for the ARM setjmp intrinsics. Instead of creating the SjLj dispatch table in IR, where it frequently violates serveral assumptions -- in particular assumptions made by the landingpad instruction about what can branch to a landing pad and what cannot. Performing this in the back-end allows us to violate these assumptions without the IR getting angry at us. It also allows us to perform a small optimization. We can shove the address of the dispatch's basic block into the function context and not have to add code around the setjmp to check for the return value and jump to the dispatch. Neat, huh? <rdar://problem/10116753> llvm-svn: 142294
Diffstat (limited to 'llvm/lib/Target')
-rw-r--r--llvm/lib/Target/ARM/ARMInstrInfo.td3
-rw-r--r--llvm/lib/Target/ARM/ARMInstrThumb.td3
-rw-r--r--llvm/lib/Target/ARM/ARMInstrThumb2.td6
3 files changed, 8 insertions, 4 deletions
diff --git a/llvm/lib/Target/ARM/ARMInstrInfo.td b/llvm/lib/Target/ARM/ARMInstrInfo.td
index 2cf0f09ffc6..669d268e6e4 100644
--- a/llvm/lib/Target/ARM/ARMInstrInfo.td
+++ b/llvm/lib/Target/ARM/ARMInstrInfo.td
@@ -4635,7 +4635,8 @@ let isCall = 1,
// no encoding information is necessary.
let Defs =
[ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR,
- QQQQ0, QQQQ1, QQQQ2, QQQQ3 ], hasSideEffects = 1, isBarrier = 1 in {
+ QQQQ0, QQQQ1, QQQQ2, QQQQ3 ], hasSideEffects = 1, isBarrier = 1,
+ usesCustomInserter = 1 in {
def Int_eh_sjlj_setjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
NoItinerary,
[(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
diff --git a/llvm/lib/Target/ARM/ARMInstrThumb.td b/llvm/lib/Target/ARM/ARMInstrThumb.td
index cedb54799db..c6cc98db66c 100644
--- a/llvm/lib/Target/ARM/ARMInstrThumb.td
+++ b/llvm/lib/Target/ARM/ARMInstrThumb.td
@@ -1259,7 +1259,8 @@ def tTPsoft : tPseudoInst<(outs), (ins), 4, IIC_Br,
// preserve all of the callee-saved resgisters, which is exactly what we want.
// $val is a scratch register for our use.
let Defs = [ R0, R1, R2, R3, R4, R5, R6, R7, R12, CPSR ],
- hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1 in
+ hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1,
+ usesCustomInserter = 1 in
def tInt_eh_sjlj_setjmp : ThumbXI<(outs),(ins tGPR:$src, tGPR:$val),
AddrModeNone, 0, NoItinerary, "","",
[(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>;
diff --git a/llvm/lib/Target/ARM/ARMInstrThumb2.td b/llvm/lib/Target/ARM/ARMInstrThumb2.td
index eb453e70852..d03a5257493 100644
--- a/llvm/lib/Target/ARM/ARMInstrThumb2.td
+++ b/llvm/lib/Target/ARM/ARMInstrThumb2.td
@@ -3088,7 +3088,8 @@ def t2CLREX : T2I<(outs), (ins), NoItinerary, "clrex", "", []>,
let Defs =
[ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR,
QQQQ0, QQQQ1, QQQQ2, QQQQ3 ],
- hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1 in {
+ hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1,
+ usesCustomInserter = 1 in {
def t2Int_eh_sjlj_setjmp : Thumb2XI<(outs), (ins tGPR:$src, tGPR:$val),
AddrModeNone, 0, NoItinerary, "", "",
[(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>,
@@ -3097,7 +3098,8 @@ let Defs =
let Defs =
[ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ],
- hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1 in {
+ hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1,
+ usesCustomInserter = 1 in {
def t2Int_eh_sjlj_setjmp_nofp : Thumb2XI<(outs), (ins tGPR:$src, tGPR:$val),
AddrModeNone, 0, NoItinerary, "", "",
[(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>,
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