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authorRafael Espindola <rafael.espindola@gmail.com>2006-08-03 17:02:20 +0000
committerRafael Espindola <rafael.espindola@gmail.com>2006-08-03 17:02:20 +0000
commita94b9e33af7ed2aca9f3466cbe17eb93cb8d586e (patch)
tree46800ff32d5af0414bfa08b7ee2dce92ab127210 /llvm/lib/Target
parentbaf6ef94c134c4d7bb47a5a773c4e73d161e185d (diff)
downloadbcm5719-llvm-a94b9e33af7ed2aca9f3466cbe17eb93cb8d586e.tar.gz
bcm5719-llvm-a94b9e33af7ed2aca9f3466cbe17eb93cb8d586e.zip
add and use ARMISD::RET_FLAG
llvm-svn: 29499
Diffstat (limited to 'llvm/lib/Target')
-rw-r--r--llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp15
-rw-r--r--llvm/lib/Target/ARM/ARMInstrInfo.td4
2 files changed, 10 insertions, 9 deletions
diff --git a/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp b/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
index 1f75cff7ffb..b299f81c01b 100644
--- a/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
+++ b/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
@@ -52,7 +52,10 @@ namespace llvm {
// Start the numbering where the builting ops and target ops leave off.
FIRST_NUMBER = ISD::BUILTIN_OP_END+ARM::INSTRUCTION_LIST_END,
/// CALL - A direct function call.
- CALL
+ CALL,
+
+ /// Return with a flag operand.
+ RET_FLAG
};
}
}
@@ -61,6 +64,7 @@ const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
switch (Opcode) {
default: return 0;
case ARMISD::CALL: return "ARMISD::CALL";
+ case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG";
}
}
@@ -175,13 +179,8 @@ static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) {
break;
}
- SDOperand LR = DAG.getRegister(ARM::R14, MVT::i32);
-
- //bug: the copy and branch should be linked with a flag so that the
- //scheduller can't move an instruction that destroys R0 in between them
- //return DAG.getNode(ISD::BRIND, MVT::Other, Copy, LR, Copy.getValue(1));
-
- return DAG.getNode(ISD::BRIND, MVT::Other, Copy, LR);
+ //We must use RET_FLAG instead of BRIND because BRIND doesn't have a flag
+ return DAG.getNode(ARMISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1));
}
static SDOperand LowerFORMAL_ARGUMENT(SDOperand Op, SelectionDAG &DAG,
diff --git a/llvm/lib/Target/ARM/ARMInstrInfo.td b/llvm/lib/Target/ARM/ARMInstrInfo.td
index a749aa00721..5ba4deba2e0 100644
--- a/llvm/lib/Target/ARM/ARMInstrInfo.td
+++ b/llvm/lib/Target/ARM/ARMInstrInfo.td
@@ -44,6 +44,8 @@ def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeq, [SDNPHasChain]
def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
[SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
+def retflag : SDNode<"ARMISD::RET_FLAG", SDTRet,
+ [SDNPHasChain, SDNPOptInFlag]>;
def ADJCALLSTACKUP : InstARM<(ops i32imm:$amt),
"!ADJCALLSTACKUP $amt",
@@ -54,7 +56,7 @@ def ADJCALLSTACKDOWN : InstARM<(ops i32imm:$amt),
[(callseq_start imm:$amt)]>;
let isReturn = 1 in {
- def bx: InstARM<(ops IntRegs:$dst), "bx $dst", [(brind IntRegs:$dst)]>;
+ def bx: InstARM<(ops), "bx r14", [(retflag)]>;
}
let Defs = [R0, R1, R2, R3] in {
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