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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2018-01-16 22:15:41 +0000 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2018-01-16 22:15:41 +0000 |
| commit | a8e6b885bdddfd8ae6faa39880dd9ba75e9b085b (patch) | |
| tree | 14d705a05640d26ef753aa372a1df813bf0e2abd /llvm/lib/Target | |
| parent | c6c89bffdc7cc238aa900f8f79ffc61f612e3d63 (diff) | |
| download | bcm5719-llvm-a8e6b885bdddfd8ae6faa39880dd9ba75e9b085b.tar.gz bcm5719-llvm-a8e6b885bdddfd8ae6faa39880dd9ba75e9b085b.zip | |
[X86][BTVER2] Fix scheduling of VCMPSD/VCMPSS instructions
For some reason they don't have a trailing i like the packed equivalents.
llvm-svn: 322600
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/X86/X86ScheduleBtVer2.td | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/Target/X86/X86ScheduleBtVer2.td b/llvm/lib/Target/X86/X86ScheduleBtVer2.td index d81a5ad3781..7f545a1c09a 100644 --- a/llvm/lib/Target/X86/X86ScheduleBtVer2.td +++ b/llvm/lib/Target/X86/X86ScheduleBtVer2.td @@ -618,7 +618,7 @@ def WriteFCmp: SchedWriteRes<[JFPU0]> { def : InstRW<[WriteFCmp], (instregex "VMAXP(D|S)rr", "VMAXS(D|S)rr")>; def : InstRW<[WriteFCmp], (instregex "VMINP(D|S)rr", "VMINS(D|S)rr")>; -def : InstRW<[WriteFCmp], (instregex "VCMPP(S|D)rri", "VCMPS(S|D)rri")>; +def : InstRW<[WriteFCmp], (instregex "VCMPP(S|D)rri", "VCMPS(S|D)rr")>; def WriteFCmpLd: SchedWriteRes<[JLAGU, JFPU0]> { let Latency = 7; @@ -626,7 +626,7 @@ def WriteFCmpLd: SchedWriteRes<[JLAGU, JFPU0]> { def : InstRW<[WriteFCmpLd], (instregex "VMAXP(D|S)rm", "VMAXS(D|S)rm")>; def : InstRW<[WriteFCmpLd], (instregex "VMINP(D|S)rm", "VMINS(D|S)rm")>; -def : InstRW<[WriteFCmpLd], (instregex "VCMPP(S|D)rmi", "VCMPS(S|D)rmi")>; +def : InstRW<[WriteFCmpLd], (instregex "VCMPP(S|D)rmi", "VCMPS(S|D)rm")>; def WriteVCVTPDY: SchedWriteRes<[JSTC, JFPU01]> { let Latency = 6; |
