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author | Daniel Sanders <daniel.sanders@imgtec.com> | 2014-06-16 13:25:35 +0000 |
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committer | Daniel Sanders <daniel.sanders@imgtec.com> | 2014-06-16 13:25:35 +0000 |
commit | a84989a22d3158f204e2c29912d745e56e39f2df (patch) | |
tree | 4df0422366239b5ab9e454ad79d224b9daed1f26 /llvm/lib/Target | |
parent | 00463119a5f9cc502c8ddd1f0e8196a3237ef400 (diff) | |
download | bcm5719-llvm-a84989a22d3158f204e2c29912d745e56e39f2df.tar.gz bcm5719-llvm-a84989a22d3158f204e2c29912d745e56e39f2df.zip |
[mips][mips64r6] ssnop is deprecated on MIPS32r6/MIPS64r6
Summary: Depends on D4120
Reviewers: jkolek, zoran.jovanovic, vmedic
Reviewed By: zoran.jovanovic, vmedic
Differential Revision: http://reviews.llvm.org/D4121
llvm-svn: 211021
Diffstat (limited to 'llvm/lib/Target')
-rw-r--r-- | llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp | 14 | ||||
-rw-r--r-- | llvm/lib/Target/Mips/Mips32r6InstrInfo.td | 1 |
2 files changed, 14 insertions, 1 deletions
diff --git a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp index b3018c96029..3133a51b3f9 100644 --- a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp +++ b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp @@ -176,6 +176,12 @@ class MipsAsmParser : public MCTargetAsmParser { bool hasMips4() const { return STI.getFeatureBits() & Mips::FeatureMips4; } bool hasMips32() const { return STI.getFeatureBits() & Mips::FeatureMips32; } + bool hasMips32r6() const { + return STI.getFeatureBits() & Mips::FeatureMips32r6; + } + bool hasMips64r6() const { + return STI.getFeatureBits() & Mips::FeatureMips64r6; + } bool parseRegister(unsigned &RegNum); @@ -905,6 +911,14 @@ bool MipsAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc, } } + // SSNOP is deprecated on MIPS32r6/MIPS64r6 + // We still accept it but it is a normal nop. + if (hasMips32r6() && Inst.getOpcode() == Mips::SSNOP) { + std::string ISA = hasMips64r6() ? "MIPS64r6" : "MIPS32r6"; + Warning(IDLoc, "ssnop is deprecated for " + ISA + " and is equivalent to a " + "nop instruction"); + } + if (MCID.hasDelaySlot() && Options.isReorder()) { // If this instruction has a delay slot and .set reorder is active, // emit a NOP after it. diff --git a/llvm/lib/Target/Mips/Mips32r6InstrInfo.td b/llvm/lib/Target/Mips/Mips32r6InstrInfo.td index cc0a595f1cb..47dafcd2960 100644 --- a/llvm/lib/Target/Mips/Mips32r6InstrInfo.td +++ b/llvm/lib/Target/Mips/Mips32r6InstrInfo.td @@ -14,7 +14,6 @@ include "Mips32r6InstrFormats.td" // Notes about removals/changes from MIPS32r6: -// Unclear: ssnop // Reencoded: jr -> jalr // Reencoded: jr.hb -> jalr.hb // Reencoded: sdbbp |