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| author | Tim Northover <tnorthover@apple.com> | 2017-07-28 17:11:01 +0000 |
|---|---|---|
| committer | Tim Northover <tnorthover@apple.com> | 2017-07-28 17:11:01 +0000 |
| commit | a7f583e33bb5432f9c03ae87411e741d7ac3c2c4 (patch) | |
| tree | bfcd8d99e0efbb9f8444226eb1c8b5a2c394c5b4 /llvm/lib/Target | |
| parent | c99209b4b24b407f8ededd3efe5b2a911ec87e5f (diff) | |
| download | bcm5719-llvm-a7f583e33bb5432f9c03ae87411e741d7ac3c2c4.tar.gz bcm5719-llvm-a7f583e33bb5432f9c03ae87411e741d7ac3c2c4.zip | |
GlobalISel: map 128-bit values to an FPR by default.
Eventually we may want to allow a pair of GPRs but absolutely nothing in the
entire world is ready for that yet.
llvm-svn: 309404
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp b/llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp index 69124dbd0f8..69f3ff6cc8c 100644 --- a/llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp +++ b/llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp @@ -488,7 +488,8 @@ AArch64RegisterBankInfo::getInstrMapping(const MachineInstr &MI) const { // As a top-level guess, vectors go in FPRs, scalars and pointers in GPRs. // For floating-point instructions, scalars go in FPRs. - if (Ty.isVector() || isPreISelGenericFloatingPointOpcode(Opc)) + if (Ty.isVector() || isPreISelGenericFloatingPointOpcode(Opc) || + Ty.getSizeInBits() > 64) OpRegBankIdx[Idx] = PMI_FirstFPR; else OpRegBankIdx[Idx] = PMI_FirstGPR; |
