diff options
| author | Chris Lattner <sabre@nondot.org> | 2007-06-09 05:01:50 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2007-06-09 05:01:50 +0000 |
| commit | a4a49e37abce58090e91a690828fa051233aba72 (patch) | |
| tree | 613bdb4dd64bb7583dba4cfb1fcdd74aec28acad /llvm/lib/Target | |
| parent | d18b16034a35bdcdbb9eb3ed9eb8d4f2fadbf502 (diff) | |
| download | bcm5719-llvm-a4a49e37abce58090e91a690828fa051233aba72.tar.gz bcm5719-llvm-a4a49e37abce58090e91a690828fa051233aba72.zip | |
fix mmx handling bug
llvm-svn: 37533
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index bf8499353fb..3f7f9f73327 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -1183,7 +1183,10 @@ X86TargetLowering::LowerX86_64CCCArguments(SDOperand Op, SelectionDAG &DAG) { RC = X86::FR64RegisterClass; else { assert(MVT::isVector(RegVT)); - RC = X86::VR128RegisterClass; + if (MVT::getSizeInBits(RegVT) == 64) + RC = X86::VR64RegisterClass; + else + RC = X86::VR128RegisterClass; } unsigned Reg = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC); |
