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author | Craig Topper <craig.topper@intel.com> | 2018-03-04 01:48:02 +0000 |
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committer | Craig Topper <craig.topper@intel.com> | 2018-03-04 01:48:02 +0000 |
commit | a476026f704450aa1474a20a6f45594488a88f9f (patch) | |
tree | e5d28d0585e0e8cb525e33af18281b75e9d38a28 /llvm/lib/Target | |
parent | be31585be861e6503bf7401d469d201f707e3f70 (diff) | |
download | bcm5719-llvm-a476026f704450aa1474a20a6f45594488a88f9f.tar.gz bcm5719-llvm-a476026f704450aa1474a20a6f45594488a88f9f.zip |
[X86] Combine (store (v1i1 (scalar_to_vector (i8 X)))) -> (store (i8 X)).
llvm-svn: 326670
Diffstat (limited to 'llvm/lib/Target')
-rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index e8b3f3656b6..d0e9b365462 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -35021,6 +35021,16 @@ static SDValue combineStore(SDNode *N, SelectionDAG &DAG, SDValue StoredVal = St->getOperand(1); const TargetLowering &TLI = DAG.getTargetLoweringInfo(); + // If this is a store of a scalar_to_vector to v1i1, just use a scalar store. + // This will avoid a copy to k-register. + if (VT == MVT::v1i1 && VT == StVT && Subtarget.hasAVX512() && + StoredVal.getOpcode() == ISD::SCALAR_TO_VECTOR && + StoredVal.getOperand(0).getValueType() == MVT::i8) { + return DAG.getStore(St->getChain(), dl, StoredVal.getOperand(0), + St->getBasePtr(), St->getPointerInfo(), + St->getAlignment(), St->getMemOperand()->getFlags()); + } + // If we are saving a concatenation of two XMM registers and 32-byte stores // are slow, such as on Sandy Bridge, perform two 16-byte stores. bool Fast; |