Rename SSARegMap -> MachineRegisterInfo in keeping with the idea

that "machine" classes are used to represent the current state of
the code being compiled.  Given this expanded name, we can start 
moving other stuff into it.  For now, move the UsedPhysRegs and
LiveIn/LoveOuts vectors from MachineFunction into it.

Update all the clients to match.

This also reduces some needless #includes, such as MachineModuleInfo
from MachineFunction.

llvm-svn: 45467

22 files changed, 189 insertions, 196 deletions

diff --git a/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp b/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
index f56043f5fdf..9b6825d1b2d 100644
--- a/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
+++ b/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
@@ -25,7 +25,6 @@
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/SelectionDAG.h"
 #include "llvm/CodeGen/SelectionDAGISel.h"
-#include "llvm/CodeGen/SSARegMap.h"
 #include "llvm/Target/TargetLowering.h"
 #include "llvm/Target/TargetOptions.h"
 #include "llvm/Support/Debug.h"
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index 0415e19c0ca..4d8a2372d01 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -24,12 +24,13 @@
 #include "llvm/Constants.h"
 #include "llvm/Instruction.h"
 #include "llvm/Intrinsics.h"
+#include "llvm/GlobalValue.h"
 #include "llvm/CodeGen/MachineBasicBlock.h"
 #include "llvm/CodeGen/MachineFrameInfo.h"
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/CodeGen/SelectionDAG.h"
-#include "llvm/CodeGen/SSARegMap.h"
 #include "llvm/Target/TargetOptions.h"
 #include "llvm/ADT/VectorExtras.h"
 #include "llvm/Support/MathExtras.h"
@@ -685,16 +686,16 @@ static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) {
                          Op.getValue(1), Sign);
     }
     Copy = DAG.getCopyToReg(Chain, ARM::R0, Op, SDOperand());
-    if (DAG.getMachineFunction().liveout_empty())
-      DAG.getMachineFunction().addLiveOut(ARM::R0);
+    if (DAG.getMachineFunction().getRegInfo().liveout_empty())
+      DAG.getMachineFunction().getRegInfo().addLiveOut(ARM::R0);
     break;
   case 5:
     Copy = DAG.getCopyToReg(Chain, ARM::R1, Op.getOperand(3), SDOperand());
     Copy = DAG.getCopyToReg(Copy, ARM::R0, Op.getOperand(1), Copy.getValue(1));
     // If we haven't noted the R0+R1 are live out, do so now.
-    if (DAG.getMachineFunction().liveout_empty()) {
-      DAG.getMachineFunction().addLiveOut(ARM::R0);
-      DAG.getMachineFunction().addLiveOut(ARM::R1);
+    if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
+      DAG.getMachineFunction().getRegInfo().addLiveOut(ARM::R0);
+      DAG.getMachineFunction().getRegInfo().addLiveOut(ARM::R1);
     }
     break;
   }
@@ -917,7 +918,7 @@ static SDOperand LowerFORMAL_ARGUMENT(SDOperand Op, SelectionDAG &DAG,
   MVT::ValueType ObjectVT = Op.getValue(ArgNo).getValueType();
   SDOperand Root = Op.getOperand(0);
   std::vector<SDOperand> ArgValues;
-  SSARegMap *RegMap = MF.getSSARegMap();
+  MachineRegisterInfo &RegInfo = MF.getRegInfo();
 
   static const unsigned GPRArgRegs[] = {
     ARM::R0, ARM::R1, ARM::R2, ARM::R3
@@ -935,20 +936,20 @@ static SDOperand LowerFORMAL_ARGUMENT(SDOperand Op, SelectionDAG &DAG,
 
   SDOperand ArgValue;
   if (ObjGPRs == 1) {
-    unsigned VReg = RegMap->createVirtualRegister(&ARM::GPRRegClass);
-    MF.addLiveIn(GPRArgRegs[NumGPRs], VReg);
+    unsigned VReg = RegInfo.createVirtualRegister(&ARM::GPRRegClass);
+    RegInfo.addLiveIn(GPRArgRegs[NumGPRs], VReg);
     vRegs[NumGPRs] = VReg;
     ArgValue = DAG.getCopyFromReg(Root, VReg, MVT::i32);
     if (ObjectVT == MVT::f32)
       ArgValue = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, ArgValue);
   } else if (ObjGPRs == 2) {
-    unsigned VReg = RegMap->createVirtualRegister(&ARM::GPRRegClass);
-    MF.addLiveIn(GPRArgRegs[NumGPRs], VReg);
+    unsigned VReg = RegInfo.createVirtualRegister(&ARM::GPRRegClass);
+    RegInfo.addLiveIn(GPRArgRegs[NumGPRs], VReg);
     vRegs[NumGPRs] = VReg;
     ArgValue = DAG.getCopyFromReg(Root, VReg, MVT::i32);
 
-    VReg = RegMap->createVirtualRegister(&ARM::GPRRegClass);
-    MF.addLiveIn(GPRArgRegs[NumGPRs+1], VReg);
+    VReg = RegInfo.createVirtualRegister(&ARM::GPRRegClass);
+    RegInfo.addLiveIn(GPRArgRegs[NumGPRs+1], VReg);
     vRegs[NumGPRs+1] = VReg;
     SDOperand ArgValue2 = DAG.getCopyFromReg(Root, VReg, MVT::i32);
 
@@ -1002,7 +1003,7 @@ ARMTargetLowering::LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG) {
     };
 
     MachineFunction &MF = DAG.getMachineFunction();
-    SSARegMap *RegMap = MF.getSSARegMap();
+    MachineRegisterInfo &RegInfo = MF.getRegInfo();
     MachineFrameInfo *MFI = MF.getFrameInfo();
     ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
     unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
@@ -1019,8 +1020,8 @@ ARMTargetLowering::LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG) {
 
       SmallVector<SDOperand, 4> MemOps;
       for (; NumGPRs < 4; ++NumGPRs) {
-        unsigned VReg = RegMap->createVirtualRegister(&ARM::GPRRegClass);
-        MF.addLiveIn(GPRArgRegs[NumGPRs], VReg);
+        unsigned VReg = RegInfo.createVirtualRegister(&ARM::GPRRegClass);
+        RegInfo.addLiveIn(GPRArgRegs[NumGPRs], VReg);
         SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::i32);
         SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
         MemOps.push_back(Store);
diff --git a/llvm/lib/Target/ARM/ARMRegisterInfo.cpp b/llvm/lib/Target/ARM/ARMRegisterInfo.cpp
index 979410a58ff..8328cef9340 100644
--- a/llvm/lib/Target/ARM/ARMRegisterInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMRegisterInfo.cpp
@@ -24,6 +24,7 @@
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/MachineLocation.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/CodeGen/RegisterScavenging.h"
 #include "llvm/Target/TargetFrameInfo.h"
 #include "llvm/Target/TargetMachine.h"
@@ -1206,14 +1207,14 @@ ARMRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
   for (unsigned i = 0; CSRegs[i]; ++i) {
     unsigned Reg = CSRegs[i];
     bool Spilled = false;
-    if (MF.isPhysRegUsed(Reg)) {
+    if (MF.getRegInfo().isPhysRegUsed(Reg)) {
       AFI->setCSRegisterIsSpilled(Reg);
       Spilled = true;
       CanEliminateFrame = false;
     } else {
       // Check alias registers too.
       for (const unsigned *Aliases = getAliasSet(Reg); *Aliases; ++Aliases) {
-        if (MF.isPhysRegUsed(*Aliases)) {
+        if (MF.getRegInfo().isPhysRegUsed(*Aliases)) {
           Spilled = true;
           CanEliminateFrame = false;
         }
@@ -1286,7 +1287,7 @@ ARMRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
     // If LR is not spilled, but at least one of R4, R5, R6, and R7 is spilled.
     // Spill LR as well so we can fold BX_RET to the registers restore (LDM).
     if (!LRSpilled && CS1Spilled) {
-      MF.setPhysRegUsed(ARM::LR);
+      MF.getRegInfo().setPhysRegUsed(ARM::LR);
       AFI->setCSRegisterIsSpilled(ARM::LR);
       NumGPRSpills++;
       UnspilledCS1GPRs.erase(std::find(UnspilledCS1GPRs.begin(),
@@ -1298,7 +1299,7 @@ ARMRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
     // Darwin ABI requires FP to point to the stack slot that contains the
     // previous FP.
     if (STI.isTargetDarwin() || hasFP(MF)) {
-      MF.setPhysRegUsed(FramePtr);
+      MF.getRegInfo().setPhysRegUsed(FramePtr);
       NumGPRSpills++;
     }
 
@@ -1312,7 +1313,7 @@ ARMRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
           unsigned Reg = UnspilledCS1GPRs[i];
           // Don't spiil high register if the function is thumb
           if (!AFI->isThumbFunction() || isLowRegister(Reg) || Reg == ARM::LR) {
-            MF.setPhysRegUsed(Reg);
+            MF.getRegInfo().setPhysRegUsed(Reg);
             AFI->setCSRegisterIsSpilled(Reg);
             if (!isReservedReg(MF, Reg))
               ExtraCSSpill = true;
@@ -1322,7 +1323,7 @@ ARMRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
       } else if (!UnspilledCS2GPRs.empty() &&
                  !AFI->isThumbFunction()) {
         unsigned Reg = UnspilledCS2GPRs.front();
-        MF.setPhysRegUsed(Reg);
+        MF.getRegInfo().setPhysRegUsed(Reg);
         AFI->setCSRegisterIsSpilled(Reg);
         if (!isReservedReg(MF, Reg))
           ExtraCSSpill = true;
@@ -1378,7 +1379,7 @@ ARMRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
         }
         if (Extras.size() && NumExtras == 0) {
           for (unsigned i = 0, e = Extras.size(); i != e; ++i) {
-            MF.setPhysRegUsed(Extras[i]);
+            MF.getRegInfo().setPhysRegUsed(Extras[i]);
             AFI->setCSRegisterIsSpilled(Extras[i]);
           }
         } else {
@@ -1392,7 +1393,7 @@ ARMRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
   }
 
   if (ForceLRSpill) {
-    MF.setPhysRegUsed(ARM::LR);
+    MF.getRegInfo().setPhysRegUsed(ARM::LR);
     AFI->setCSRegisterIsSpilled(ARM::LR);
     AFI->setLRIsSpilledForFarJump(true);
   }
@@ -1446,9 +1447,9 @@ void ARMRegisterInfo::emitPrologue(MachineFunction &MF) const {
 
   if (isThumb) {
     // Check if R3 is live in. It might have to be used as a scratch register.
-    for (MachineFunction::livein_iterator I=MF.livein_begin(),E=MF.livein_end();
-         I != E; ++I) {
-      if ((*I).first == ARM::R3) {
+    for (MachineRegisterInfo::livein_iterator I =MF.getRegInfo().livein_begin(),
+         E = MF.getRegInfo().livein_end(); I != E; ++I) {
+      if (I->first == ARM::R3) {
         AFI->setR3IsLiveIn(true);
         break;
       }
diff --git a/llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp b/llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
index 4b756b65821..0490f88bb4a 100644
--- a/llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
+++ b/llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
@@ -18,7 +18,7 @@
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/MachineFrameInfo.h"
 #include "llvm/CodeGen/MachineFunction.h"
-#include "llvm/CodeGen/SSARegMap.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/CodeGen/SelectionDAG.h"
 #include "llvm/CodeGen/SelectionDAGISel.h"
 #include "llvm/Target/TargetOptions.h"
@@ -200,10 +200,9 @@ private:
 /// GOT address into a register.
 ///
 SDOperand AlphaDAGToDAGISel::getGlobalBaseReg() {
-  MachineFunction* MF = BB->getParent();
   unsigned GP = 0;
-  for(MachineFunction::livein_iterator ii = MF->livein_begin(), 
-        ee = MF->livein_end(); ii != ee; ++ii)
+  for(MachineRegisterInfo::livein_iterator ii = RegInfo->livein_begin(), 
+        ee = RegInfo->livein_end(); ii != ee; ++ii)
     if (ii->first == Alpha::R29) {
       GP = ii->second;
       break;
@@ -216,10 +215,9 @@ SDOperand AlphaDAGToDAGISel::getGlobalBaseReg() {
 /// getRASaveReg - Grab the return address
 ///
 SDOperand AlphaDAGToDAGISel::getGlobalRetAddr() {
-  MachineFunction* MF = BB->getParent();
   unsigned RA = 0;
-  for(MachineFunction::livein_iterator ii = MF->livein_begin(), 
-        ee = MF->livein_end(); ii != ee; ++ii)
+  for(MachineRegisterInfo::livein_iterator ii = RegInfo->livein_begin(), 
+        ee = RegInfo->livein_end(); ii != ee; ++ii)
     if (ii->first == Alpha::R26) {
       RA = ii->second;
       break;
diff --git a/llvm/lib/Target/Alpha/AlphaISelLowering.cpp b/llvm/lib/Target/Alpha/AlphaISelLowering.cpp
index 295b456c0d2..a37e8861bbc 100644
--- a/llvm/lib/Target/Alpha/AlphaISelLowering.cpp
+++ b/llvm/lib/Target/Alpha/AlphaISelLowering.cpp
@@ -16,8 +16,9 @@
 #include "llvm/CodeGen/MachineFrameInfo.h"
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/CodeGen/SelectionDAG.h"
-#include "llvm/CodeGen/SSARegMap.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/Constants.h"
 #include "llvm/Function.h"
 #include "llvm/Module.h"
@@ -30,8 +31,8 @@ using namespace llvm;
 static unsigned AddLiveIn(MachineFunction &MF, unsigned PReg,
                           TargetRegisterClass *RC) {
   assert(RC->contains(PReg) && "Not the correct regclass!");
-  unsigned VReg = MF.getSSARegMap()->createVirtualRegister(RC);
-  MF.addLiveIn(PReg, VReg);
+  unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
+  MF.getRegInfo().addLiveIn(PReg, VReg);
   return VReg;
 }
 
@@ -312,8 +313,8 @@ static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) {
       ArgReg = Alpha::F0;
     }
     Copy = DAG.getCopyToReg(Copy, ArgReg, Op.getOperand(1), Copy.getValue(1));
-    if (DAG.getMachineFunction().liveout_empty())
-      DAG.getMachineFunction().addLiveOut(ArgReg);
+    if (DAG.getMachineFunction().getRegInfo().liveout_empty())
+      DAG.getMachineFunction().getRegInfo().addLiveOut(ArgReg);
     break;
   }
   }
diff --git a/llvm/lib/Target/CellSPU/SPUISelDAGToDAG.cpp b/llvm/lib/Target/CellSPU/SPUISelDAGToDAG.cpp
index acd0c8bbfc8..73e46fff1be 100644
--- a/llvm/lib/Target/CellSPU/SPUISelDAGToDAG.cpp
+++ b/llvm/lib/Target/CellSPU/SPUISelDAGToDAG.cpp
@@ -20,7 +20,6 @@
 #include "llvm/CodeGen/MachineConstantPool.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/MachineFunction.h"
-#include "llvm/CodeGen/SSARegMap.h"
 #include "llvm/CodeGen/SelectionDAG.h"
 #include "llvm/CodeGen/SelectionDAGISel.h"
 #include "llvm/Target/TargetOptions.h"
diff --git a/llvm/lib/Target/CellSPU/SPUISelLowering.cpp b/llvm/lib/Target/CellSPU/SPUISelLowering.cpp
index 941cde12378..7893e677fbb 100644
--- a/llvm/lib/Target/CellSPU/SPUISelLowering.cpp
+++ b/llvm/lib/Target/CellSPU/SPUISelLowering.cpp
@@ -20,8 +20,8 @@
 #include "llvm/CodeGen/MachineFrameInfo.h"
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/CodeGen/SelectionDAG.h"
-#include "llvm/CodeGen/SSARegMap.h"
 #include "llvm/Constants.h"
 #include "llvm/Function.h"
 #include "llvm/Intrinsics.h"
@@ -902,7 +902,7 @@ LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG, int &VarArgsFrameIndex)
 {
   MachineFunction &MF = DAG.getMachineFunction();
   MachineFrameInfo *MFI = MF.getFrameInfo();
-  SSARegMap *RegMap = MF.getSSARegMap();
+  MachineRegisterInfo &RegInfo = MF.getRegInfo();
   SmallVector<SDOperand, 8> ArgValues;
   SDOperand Root = Op.getOperand(0);
   bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
@@ -932,8 +932,8 @@ LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG, int &VarArgsFrameIndex)
     }
     case MVT::i8:
       if (!isVarArg && ArgRegIdx < NumArgRegs) {
-        unsigned VReg = RegMap->createVirtualRegister(&SPU::R8CRegClass);
-        MF.addLiveIn(ArgRegs[ArgRegIdx], VReg);
+        unsigned VReg = RegInfo.createVirtualRegister(&SPU::R8CRegClass);
+        RegInfo.addLiveIn(ArgRegs[ArgRegIdx], VReg);
         ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::i8);
         ++ArgRegIdx;
       } else {
@@ -942,8 +942,8 @@ LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG, int &VarArgsFrameIndex)
       break;
     case MVT::i16:
       if (!isVarArg && ArgRegIdx < NumArgRegs) {
-        unsigned VReg = RegMap->createVirtualRegister(&SPU::R16CRegClass);
-        MF.addLiveIn(ArgRegs[ArgRegIdx], VReg);
+        unsigned VReg = RegInfo.createVirtualRegister(&SPU::R16CRegClass);
+        RegInfo.addLiveIn(ArgRegs[ArgRegIdx], VReg);
         ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::i16);
         ++ArgRegIdx;
       } else {
@@ -952,8 +952,8 @@ LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG, int &VarArgsFrameIndex)
       break;
     case MVT::i32:
       if (!isVarArg && ArgRegIdx < NumArgRegs) {
-        unsigned VReg = RegMap->createVirtualRegister(&SPU::R32CRegClass);
-        MF.addLiveIn(ArgRegs[ArgRegIdx], VReg);
+        unsigned VReg = RegInfo.createVirtualRegister(&SPU::R32CRegClass);
+        RegInfo.addLiveIn(ArgRegs[ArgRegIdx], VReg);
         ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::i32);
         ++ArgRegIdx;
       } else {
@@ -962,8 +962,8 @@ LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG, int &VarArgsFrameIndex)
       break;
     case MVT::i64:
       if (!isVarArg && ArgRegIdx < NumArgRegs) {
-        unsigned VReg = RegMap->createVirtualRegister(&SPU::R64CRegClass);
-        MF.addLiveIn(ArgRegs[ArgRegIdx], VReg);
+        unsigned VReg = RegInfo.createVirtualRegister(&SPU::R64CRegClass);
+        RegInfo.addLiveIn(ArgRegs[ArgRegIdx], VReg);
         ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::i64);
         ++ArgRegIdx;
       } else {
@@ -972,8 +972,8 @@ LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG, int &VarArgsFrameIndex)
       break;
     case MVT::f32:
       if (!isVarArg && ArgRegIdx < NumArgRegs) {
-        unsigned VReg = RegMap->createVirtualRegister(&SPU::R32FPRegClass);
-        MF.addLiveIn(ArgRegs[ArgRegIdx], VReg);
+        unsigned VReg = RegInfo.createVirtualRegister(&SPU::R32FPRegClass);
+        RegInfo.addLiveIn(ArgRegs[ArgRegIdx], VReg);
         ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::f32);
         ++ArgRegIdx;
       } else {
@@ -982,8 +982,8 @@ LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG, int &VarArgsFrameIndex)
       break;
     case MVT::f64:
       if (!isVarArg && ArgRegIdx < NumArgRegs) {
-        unsigned VReg = RegMap->createVirtualRegister(&SPU::R64FPRegClass);
-        MF.addLiveIn(ArgRegs[ArgRegIdx], VReg);
+        unsigned VReg = RegInfo.createVirtualRegister(&SPU::R64FPRegClass);
+        RegInfo.addLiveIn(ArgRegs[ArgRegIdx], VReg);
         ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::f64);
         ++ArgRegIdx;
       } else {
@@ -996,8 +996,8 @@ LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG, int &VarArgsFrameIndex)
     case MVT::v8i16:
     case MVT::v16i8:
       if (!isVarArg && ArgRegIdx < NumArgRegs) {
-        unsigned VReg = RegMap->createVirtualRegister(&SPU::VECREGRegClass);
-        MF.addLiveIn(ArgRegs[ArgRegIdx], VReg);
+        unsigned VReg = RegInfo.createVirtualRegister(&SPU::VECREGRegClass);
+        RegInfo.addLiveIn(ArgRegs[ArgRegIdx], VReg);
         ArgVal = DAG.getCopyFromReg(Root, VReg, ObjectVT);
         ++ArgRegIdx;
       } else {
@@ -1037,8 +1037,8 @@ LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG, int &VarArgsFrameIndex)
     // result of va_next.
     SmallVector<SDOperand, 8> MemOps;
     for (; ArgRegIdx != NumArgRegs; ++ArgRegIdx) {
-      unsigned VReg = RegMap->createVirtualRegister(&SPU::GPRCRegClass);
-      MF.addLiveIn(ArgRegs[ArgRegIdx], VReg);
+      unsigned VReg = RegInfo.createVirtualRegister(&SPU::GPRCRegClass);
+      RegInfo.addLiveIn(ArgRegs[ArgRegIdx], VReg);
       SDOperand Val = DAG.getCopyFromReg(Root, VReg, PtrVT);
       SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
       MemOps.push_back(Store);
@@ -1294,9 +1294,9 @@ LowerRET(SDOperand Op, SelectionDAG &DAG, TargetMachine &TM) {
   
   // If this is the first return lowered for this function, add the regs to the
   // liveout set for the function.
-  if (DAG.getMachineFunction().liveout_empty()) {
+  if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
     for (unsigned i = 0; i != RVLocs.size(); ++i)
-      DAG.getMachineFunction().addLiveOut(RVLocs[i].getLocReg());
+      DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
   }
 
   SDOperand Chain = Op.getOperand(0);
@@ -1785,8 +1785,8 @@ static SDOperand LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG) {
   if (EltsFromV2 == 1 && monotonic) {
     // Compute mask and shuffle
     MachineFunction &MF = DAG.getMachineFunction();
-    SSARegMap *RegMap = MF.getSSARegMap();
-    unsigned VReg = RegMap->createVirtualRegister(&SPU::R32CRegClass);
+    MachineRegisterInfo &RegInfo = MF.getRegInfo();
+    unsigned VReg = RegInfo.createVirtualRegister(&SPU::R32CRegClass);
     MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
     // Initialize temporary register to 0
     SDOperand InitTempReg =
@@ -1893,12 +1893,12 @@ static SDOperand LowerVectorMUL(SDOperand Op, SelectionDAG &DAG) {
   // the wacky side
   case MVT::v8i16: {
     MachineFunction &MF = DAG.getMachineFunction();
-    SSARegMap *RegMap = MF.getSSARegMap();
+    MachineRegisterInfo &RegInfo = MF.getRegInfo();
     SDOperand Chain = Op.getOperand(0);
     SDOperand rA = Op.getOperand(0);
     SDOperand rB = Op.getOperand(1);
-    unsigned FSMBIreg = RegMap->createVirtualRegister(&SPU::VECREGRegClass);
-    unsigned HiProdReg = RegMap->createVirtualRegister(&SPU::VECREGRegClass);
+    unsigned FSMBIreg = RegInfo.createVirtualRegister(&SPU::VECREGRegClass);
+    unsigned HiProdReg = RegInfo.createVirtualRegister(&SPU::VECREGRegClass);
 
     SDOperand FSMBOp =
       DAG.getCopyToReg(Chain, FSMBIreg,
@@ -1929,16 +1929,16 @@ static SDOperand LowerVectorMUL(SDOperand Op, SelectionDAG &DAG) {
   // intermediate products.
   case MVT::v16i8: {
     MachineFunction &MF = DAG.getMachineFunction();
-    SSARegMap *RegMap = MF.getSSARegMap();
+    MachineRegisterInfo &RegInfo = MF.getRegInfo();
     SDOperand Chain = Op.getOperand(0);
     SDOperand rA = Op.getOperand(0);
     SDOperand rB = Op.getOperand(1);
     SDOperand c8 = DAG.getConstant(8, MVT::i8);
     SDOperand c16 = DAG.getConstant(16, MVT::i8);
 
-    unsigned FSMBreg_2222 = RegMap->createVirtualRegister(&SPU::VECREGRegClass);
-    unsigned LoProd_reg = RegMap->createVirtualRegister(&SPU::VECREGRegClass);
-    unsigned HiProd_reg = RegMap->createVirtualRegister(&SPU::VECREGRegClass);
+    unsigned FSMBreg_2222 = RegInfo.createVirtualRegister(&SPU::VECREGRegClass);
+    unsigned LoProd_reg = RegInfo.createVirtualRegister(&SPU::VECREGRegClass);
+    unsigned HiProd_reg = RegInfo.createVirtualRegister(&SPU::VECREGRegClass);
 
     SDOperand LLProd =
       DAG.getNode(SPUISD::MPY, MVT::v8i16,
@@ -2024,7 +2024,7 @@ static SDOperand LowerVectorMUL(SDOperand Op, SelectionDAG &DAG) {
 
 static SDOperand LowerFDIVf32(SDOperand Op, SelectionDAG &DAG) {
   MachineFunction &MF = DAG.getMachineFunction();
-  SSARegMap *RegMap = MF.getSSARegMap();
+  MachineRegisterInfo &RegInfo = MF.getRegInfo();
 
   SDOperand A = Op.getOperand(0);
   SDOperand B = Op.getOperand(1);
@@ -2033,11 +2033,11 @@ static SDOperand LowerFDIVf32(SDOperand Op, SelectionDAG &DAG) {
   unsigned VRegBR, VRegC;
 
   if (VT == MVT::f32) {
-    VRegBR = RegMap->createVirtualRegister(&SPU::R32FPRegClass);
-    VRegC = RegMap->createVirtualRegister(&SPU::R32FPRegClass);
+    VRegBR = RegInfo.createVirtualRegister(&SPU::R32FPRegClass);
+    VRegC = RegInfo.createVirtualRegister(&SPU::R32FPRegClass);
   } else {
-    VRegBR = RegMap->createVirtualRegister(&SPU::VECREGRegClass);
-    VRegC = RegMap->createVirtualRegister(&SPU::VECREGRegClass);
+    VRegBR = RegInfo.createVirtualRegister(&SPU::VECREGRegClass);
+    VRegC = RegInfo.createVirtualRegister(&SPU::VECREGRegClass);
   }
   // TODO: make sure we're feeding FPInterp the right arguments
   // Right now: fi B, frest(B)
@@ -2066,18 +2066,6 @@ static SDOperand LowerFDIVf32(SDOperand Op, SelectionDAG &DAG) {
 			    DAG.getCopyFromReg(AxBRcpl, VRegC, VT)))));
 }
 
-// Expands double-precision FDIV
-// Expects two doubles as inputs X and Y, does a floating point
-// reciprocal estimate, and three iterations of Newton-Raphson
-// to increase accuracy.
-//static SDOperand LowerFDIVf64(SDOperand Op, SelectionDAG &DAG) {
-//  MachineFunction &MF = DAG.getMachineFunction();
-//  SSARegMap *RegMap = MF.getSSARegMap();
-//
-//  SDOperand X = Op.getOperand(0);
-//  SDOperand Y = Op.getOperand(1);
-//}
-
 static SDOperand LowerEXTRACT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG) {
   unsigned VT = Op.getValueType();
   SDOperand N = Op.getOperand(0);
@@ -2365,9 +2353,9 @@ static SDOperand LowerCTPOP(SDOperand Op, SelectionDAG &DAG) {
 
   case MVT::i16: {
     MachineFunction &MF = DAG.getMachineFunction();
-    SSARegMap *RegMap = MF.getSSARegMap();
+    MachineRegisterInfo &RegInfo = MF.getRegInfo();
 
-    unsigned CNTB_reg = RegMap->createVirtualRegister(&SPU::R16CRegClass);
+    unsigned CNTB_reg = RegInfo.createVirtualRegister(&SPU::R16CRegClass);
 
     SDOperand N = Op.getOperand(0);
     SDOperand Elt0 = DAG.getConstant(0, MVT::i16);
@@ -2397,10 +2385,10 @@ static SDOperand LowerCTPOP(SDOperand Op, SelectionDAG &DAG) {
 
   case MVT::i32: {
     MachineFunction &MF = DAG.getMachineFunction();
-    SSARegMap *RegMap = MF.getSSARegMap();
+    MachineRegisterInfo &RegInfo = MF.getRegInfo();
 
-    unsigned CNTB_reg = RegMap->createVirtualRegister(&SPU::R32CRegClass);
-    unsigned SUM1_reg = RegMap->createVirtualRegister(&SPU::R32CRegClass);
+    unsigned CNTB_reg = RegInfo.createVirtualRegister(&SPU::R32CRegClass);
+    unsigned SUM1_reg = RegInfo.createVirtualRegister(&SPU::R32CRegClass);
 
     SDOperand N = Op.getOperand(0);
     SDOperand Elt0 = DAG.getConstant(0, MVT::i32);
diff --git a/llvm/lib/Target/CellSPU/SPURegisterInfo.cpp b/llvm/lib/Target/CellSPU/SPURegisterInfo.cpp
index 9f8dbeede76..ec886d56804 100644
--- a/llvm/lib/Target/CellSPU/SPURegisterInfo.cpp
+++ b/llvm/lib/Target/CellSPU/SPURegisterInfo.cpp
@@ -27,6 +27,7 @@
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/MachineFrameInfo.h"
 #include "llvm/CodeGen/MachineLocation.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/CodeGen/SelectionDAGNodes.h"
 #include "llvm/CodeGen/ValueTypes.h"
 #include "llvm/Target/TargetFrameInfo.h"
@@ -670,15 +671,15 @@ void SPURegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
 #if 0
   //  Save and clear the LR state.
   SPUFunctionInfo *FI = MF.getInfo<SPUFunctionInfo>();
-  FI->setUsesLR(MF.isPhysRegUsed(LR));
+  FI->setUsesLR(MF.getRegInfo().isPhysRegUsed(LR));
 #endif
   // Mark LR and SP unused, since the prolog spills them to stack and
   // we don't want anyone else to spill them for us.
   //
   // Also, unless R2 is really used someday, don't spill it automatically.
-  MF.setPhysRegUnused(SPU::R0);
-  MF.setPhysRegUnused(SPU::R1);
-  MF.setPhysRegUnused(SPU::R2);
+  MF.getRegInfo().setPhysRegUnused(SPU::R0);
+  MF.getRegInfo().setPhysRegUnused(SPU::R1);
+  MF.getRegInfo().setPhysRegUnused(SPU::R2);
 }
 
 void SPURegisterInfo::emitPrologue(MachineFunction &MF) const
diff --git a/llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp b/llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
index 0d9aeb3ac46..af31aaf555e 100644
--- a/llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
@@ -18,7 +18,6 @@
 #include "IA64ISelLowering.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/MachineFunction.h"
-#include "llvm/CodeGen/SSARegMap.h"
 #include "llvm/CodeGen/SelectionDAG.h"
 #include "llvm/CodeGen/SelectionDAGISel.h"
 #include "llvm/Target/TargetOptions.h"
diff --git a/llvm/lib/Target/IA64/IA64ISelLowering.cpp b/llvm/lib/Target/IA64/IA64ISelLowering.cpp
index c02cd1bcc74..b6b6c256e4e 100644
--- a/llvm/lib/Target/IA64/IA64ISelLowering.cpp
+++ b/llvm/lib/Target/IA64/IA64ISelLowering.cpp
@@ -18,7 +18,7 @@
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/SelectionDAG.h"
-#include "llvm/CodeGen/SSARegMap.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/Constants.h"
 #include "llvm/Function.h"
 using namespace llvm;
@@ -148,9 +148,9 @@ IA64TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
   MachineFrameInfo *MFI = MF.getFrameInfo();
   const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
   
-  GP = MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i64));
-  SP = MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i64));
-  RP = MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i64));
+  GP = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
+  SP = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
+  RP = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
   
   MachineBasicBlock& BB = MF.front();
 
@@ -182,10 +182,11 @@ IA64TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
             // see intel ABI docs)
           case MVT::f64:
 //XXX            BuildMI(&BB, IA64::IDEF, 0, args_FP[used_FPArgs]);
-            MF.addLiveIn(args_FP[used_FPArgs]); // mark this reg as liveIn
+            MF.getRegInfo().addLiveIn(args_FP[used_FPArgs]);
+            // mark this reg as liveIn
             // floating point args go into f8..f15 as-needed, the increment
             argVreg[count] =                              // is below..:
-            MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::f64));
+            MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::f64));
             // FP args go into f8..f15 as needed: (hence the ++)
             argPreg[count] = args_FP[used_FPArgs++];
             argOpc[count] = IA64::FMOV;
@@ -201,9 +202,10 @@ IA64TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
           case MVT::i32:
           case MVT::i64:
 //XXX            BuildMI(&BB, IA64::IDEF, 0, args_int[count]);
-            MF.addLiveIn(args_int[count]); // mark this register as liveIn
+            MF.getRegInfo().addLiveIn(args_int[count]);
+            // mark this register as liveIn
             argVreg[count] =
-            MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i64));
+            MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
             argPreg[count] = args_int[count];
             argOpc[count] = IA64::MOV;
             argt = newroot =
@@ -232,7 +234,7 @@ IA64TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
 
   // Create a vreg to hold the output of (what will become)
   // the "alloc" instruction
-  VirtGPR = MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i64));
+  VirtGPR = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
   BuildMI(&BB, TII->get(IA64::PSEUDO_ALLOC), VirtGPR);
   // we create a PSEUDO_ALLOC (pseudo)instruction for now
 /*
@@ -284,11 +286,11 @@ IA64TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
   case MVT::i16:
   case MVT::i32:
   case MVT::i64:
-    MF.addLiveOut(IA64::r8);
+    MF.getRegInfo().addLiveOut(IA64::r8);
     break;
   case MVT::f32:
   case MVT::f64:
-    MF.addLiveOut(IA64::F8);
+    MF.getRegInfo().addLiveOut(IA64::F8);
     break;
   }
 
diff --git a/llvm/lib/Target/IA64/IA64RegisterInfo.cpp b/llvm/lib/Target/IA64/IA64RegisterInfo.cpp
index e00625c9740..b570824594c 100644
--- a/llvm/lib/Target/IA64/IA64RegisterInfo.cpp
+++ b/llvm/lib/Target/IA64/IA64RegisterInfo.cpp
@@ -23,11 +23,11 @@
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/MachineFrameInfo.h"
 #include "llvm/CodeGen/MachineLocation.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/Target/TargetFrameInfo.h"
 #include "llvm/Target/TargetMachine.h"
 #include "llvm/Target/TargetOptions.h"
 #include "llvm/Target/TargetInstrInfo.h"
-#include "llvm/Support/CommandLine.h"
 #include "llvm/ADT/BitVector.h"
 #include "llvm/ADT/STLExtras.h"
 using namespace llvm;
@@ -328,8 +328,8 @@ void IA64RegisterInfo::emitPrologue(MachineFunction &MF) const {
         IA64::r126, IA64::r127 };
 
   unsigned numStackedGPRsUsed=0;
-  for(int i=0; i<96; i++) {
-    if(MF.isPhysRegUsed(RegsInOrder[i]))
+  for (int i=0; i != 96; i++) {
+    if (MF.getRegInfo().isPhysRegUsed(RegsInOrder[i]))
       numStackedGPRsUsed=i+1; // (i+1 and not ++ - consider fn(fp, fp, int)
   }
 
diff --git a/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp b/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
index 07330ee110f..b2ad66670bb 100644
--- a/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
+++ b/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
@@ -12,7 +12,6 @@
 //===----------------------------------------------------------------------===//
 
 #define DEBUG_TYPE "mips-isel"
-
 #include "Mips.h"
 #include "MipsISelLowering.h"
 #include "MipsMachineFunction.h"
@@ -28,6 +27,7 @@
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/MachineFrameInfo.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/CodeGen/SelectionDAGISel.h"
 #include "llvm/Target/TargetMachine.h"
 #include "llvm/Support/Compiler.h"
@@ -127,12 +127,11 @@ InstructionSelectBasicBlock(SelectionDAG &SD)
 
 /// getGlobalBaseReg - Output the instructions required to put the
 /// GOT address into a register.
-SDOperand MipsDAGToDAGISel::getGlobalBaseReg() 
-{
+SDOperand MipsDAGToDAGISel::getGlobalBaseReg() {
   MachineFunction* MF = BB->getParent();
   unsigned GP = 0;
-  for(MachineFunction::livein_iterator ii = MF->livein_begin(), 
-        ee = MF->livein_end(); ii != ee; ++ii)
+  for(MachineRegisterInfo::livein_iterator ii = MF->getRegInfo().livein_begin(),
+        ee = MF->getRegInfo().livein_end(); ii != ee; ++ii)
     if (ii->first == Mips::GP) {
       GP = ii->second;
       break;
diff --git a/llvm/lib/Target/Mips/MipsISelLowering.cpp b/llvm/lib/Target/Mips/MipsISelLowering.cpp
index d17c980b372..56527ebc339 100644
--- a/llvm/lib/Target/Mips/MipsISelLowering.cpp
+++ b/llvm/lib/Target/Mips/MipsISelLowering.cpp
@@ -25,8 +25,8 @@
 #include "llvm/CodeGen/MachineFrameInfo.h"
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/CodeGen/SelectionDAGISel.h"
-#include "llvm/CodeGen/SSARegMap.h"
 #include "llvm/CodeGen/ValueTypes.h"
 #include "llvm/Support/Debug.h"
 #include <queue>
@@ -139,8 +139,8 @@ static unsigned
 AddLiveIn(MachineFunction &MF, unsigned PReg, TargetRegisterClass *RC) 
 {
   assert(RC->contains(PReg) && "Not the correct regclass!");
-  unsigned VReg = MF.getSSARegMap()->createVirtualRegister(RC);
-  MF.addLiveIn(PReg, VReg);
+  unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
+  MF.getRegInfo().addLiveIn(PReg, VReg);
   return VReg;
 }
 
@@ -596,10 +596,10 @@ LowerRET(SDOperand Op, SelectionDAG &DAG)
 
   // If this is the first return lowered for this function, add 
   // the regs to the liveout set for the function.
-  if (DAG.getMachineFunction().liveout_empty()) {
+  if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
     for (unsigned i = 0; i != RVLocs.size(); ++i)
       if (RVLocs[i].isRegLoc())
-        DAG.getMachineFunction().addLiveOut(RVLocs[i].getLocReg());
+        DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
   }
 
   // The chain is always operand #0
diff --git a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
index 767fd99914c..2c5e3fcdd81 100644
--- a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
@@ -20,7 +20,7 @@
 #include "PPCHazardRecognizers.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/MachineFunction.h"
-#include "llvm/CodeGen/SSARegMap.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/CodeGen/SelectionDAG.h"
 #include "llvm/CodeGen/SelectionDAGISel.h"
 #include "llvm/Target/TargetOptions.h"
@@ -224,11 +224,10 @@ void PPCDAGToDAGISel::InsertVRSaveCode(Function &F) {
   // In this case, there will be virtual registers of vector type type created
   // by the scheduler.  Detect them now.
   MachineFunction &Fn = MachineFunction::get(&F);
-  SSARegMap *RegMap = Fn.getSSARegMap();
   bool HasVectorVReg = false;
   for (unsigned i = MRegisterInfo::FirstVirtualRegister, 
-       e = RegMap->getLastVirtReg()+1; i != e; ++i)
-    if (RegMap->getRegClass(i) == &PPC::VRRCRegClass) {
+       e = RegInfo->getLastVirtReg()+1; i != e; ++i)
+    if (RegInfo->getRegClass(i) == &PPC::VRRCRegClass) {
       HasVectorVReg = true;
       break;
     }
@@ -246,8 +245,8 @@ void PPCDAGToDAGISel::InsertVRSaveCode(Function &F) {
 
   // Create two vregs - one to hold the VRSAVE register that is live-in to the
   // function and one for the value after having bits or'd into it.
-  unsigned InVRSAVE = RegMap->createVirtualRegister(&PPC::GPRCRegClass);
-  unsigned UpdatedVRSAVE = RegMap->createVirtualRegister(&PPC::GPRCRegClass);
+  unsigned InVRSAVE = RegInfo->createVirtualRegister(&PPC::GPRCRegClass);
+  unsigned UpdatedVRSAVE = RegInfo->createVirtualRegister(&PPC::GPRCRegClass);
   
   const TargetInstrInfo &TII = *TM.getInstrInfo();
   MachineBasicBlock &EntryBB = *Fn.begin();
@@ -287,14 +286,13 @@ SDNode *PPCDAGToDAGISel::getGlobalBaseReg() {
     // Insert the set of GlobalBaseReg into the first MBB of the function
     MachineBasicBlock &FirstMBB = BB->getParent()->front();
     MachineBasicBlock::iterator MBBI = FirstMBB.begin();
-    SSARegMap *RegMap = BB->getParent()->getSSARegMap();
 
     if (PPCLowering.getPointerTy() == MVT::i32) {
-      GlobalBaseReg = RegMap->createVirtualRegister(PPC::GPRCRegisterClass);
+      GlobalBaseReg = RegInfo->createVirtualRegister(PPC::GPRCRegisterClass);
       BuildMI(FirstMBB, MBBI, TII.get(PPC::MovePCtoLR), PPC::LR);
       BuildMI(FirstMBB, MBBI, TII.get(PPC::MFLR), GlobalBaseReg);
     } else {
-      GlobalBaseReg = RegMap->createVirtualRegister(PPC::G8RCRegisterClass);
+      GlobalBaseReg = RegInfo->createVirtualRegister(PPC::G8RCRegisterClass);
       BuildMI(FirstMBB, MBBI, TII.get(PPC::MovePCtoLR8), PPC::LR8);
       BuildMI(FirstMBB, MBBI, TII.get(PPC::MFLR8), GlobalBaseReg);
     }
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index 0ac16823730..66915eb9ae6 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -23,8 +23,8 @@
 #include "llvm/CodeGen/MachineFrameInfo.h"
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/CodeGen/SelectionDAG.h"
-#include "llvm/CodeGen/SSARegMap.h"
 #include "llvm/Constants.h"
 #include "llvm/Function.h"
 #include "llvm/Intrinsics.h"
@@ -1265,7 +1265,7 @@ static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG,
   //
   MachineFunction &MF = DAG.getMachineFunction();
   MachineFrameInfo *MFI = MF.getFrameInfo();
-  SSARegMap *RegMap = MF.getSSARegMap();
+  MachineRegisterInfo &RegInfo = MF.getRegInfo();
   SmallVector<SDOperand, 8> ArgValues;
   SDOperand Root = Op.getOperand(0);
   
@@ -1329,8 +1329,8 @@ static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG,
       // Double word align in ELF
       if (Expand && isELF32_ABI) GPR_idx += (GPR_idx % 2);
       if (GPR_idx != Num_GPR_Regs) {
-        unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass);
-        MF.addLiveIn(GPR[GPR_idx], VReg);
+        unsigned VReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass);
+        RegInfo.addLiveIn(GPR[GPR_idx], VReg);
         ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::i32);
         ++GPR_idx;
       } else {
@@ -1346,8 +1346,8 @@ static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG,
       
     case MVT::i64:  // PPC64
       if (GPR_idx != Num_GPR_Regs) {
-        unsigned VReg = RegMap->createVirtualRegister(&PPC::G8RCRegClass);
-        MF.addLiveIn(GPR[GPR_idx], VReg);
+        unsigned VReg = RegInfo.createVirtualRegister(&PPC::G8RCRegClass);
+        RegInfo.addLiveIn(GPR[GPR_idx], VReg);
         ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::i64);
         ++GPR_idx;
       } else {
@@ -1369,10 +1369,10 @@ static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG,
       if (FPR_idx != Num_FPR_Regs) {
         unsigned VReg;
         if (ObjectVT == MVT::f32)
-          VReg = RegMap->createVirtualRegister(&PPC::F4RCRegClass);
+          VReg = RegInfo.createVirtualRegister(&PPC::F4RCRegClass);
         else
-          VReg = RegMap->createVirtualRegister(&PPC::F8RCRegClass);
-        MF.addLiveIn(FPR[FPR_idx], VReg);
+          VReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass);
+        RegInfo.addLiveIn(FPR[FPR_idx], VReg);
         ArgVal = DAG.getCopyFromReg(Root, VReg, ObjectVT);
         ++FPR_idx;
       } else {
@@ -1391,8 +1391,8 @@ static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG,
     case MVT::v16i8:
       // Note that vector arguments in registers don't reserve stack space.
       if (VR_idx != Num_VR_Regs) {
-        unsigned VReg = RegMap->createVirtualRegister(&PPC::VRRCRegClass);
-        MF.addLiveIn(VR[VR_idx], VReg);
+        unsigned VReg = RegInfo.createVirtualRegister(&PPC::VRRCRegClass);
+        RegInfo.addLiveIn(VR[VR_idx], VReg);
         ArgVal = DAG.getCopyFromReg(Root, VReg, ObjectVT);
         ++VR_idx;
       } else {
@@ -1471,11 +1471,11 @@ static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG,
     for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
       unsigned VReg;
       if (isPPC64)
-        VReg = RegMap->createVirtualRegister(&PPC::G8RCRegClass);
+        VReg = RegInfo.createVirtualRegister(&PPC::G8RCRegClass);
       else
-        VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass);
+        VReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass);
 
-      MF.addLiveIn(GPR[GPR_idx], VReg);
+      RegInfo.addLiveIn(GPR[GPR_idx], VReg);
       SDOperand Val = DAG.getCopyFromReg(Root, VReg, PtrVT);
       SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
       MemOps.push_back(Store);
@@ -1499,9 +1499,9 @@ static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG,
 
       for (; FPR_idx != Num_FPR_Regs; ++FPR_idx) {
         unsigned VReg;
-        VReg = RegMap->createVirtualRegister(&PPC::F8RCRegClass);
+        VReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass);
 
-        MF.addLiveIn(FPR[FPR_idx], VReg);
+        RegInfo.addLiveIn(FPR[FPR_idx], VReg);
         SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::f64);
         SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
         MemOps.push_back(Store);
@@ -1905,9 +1905,9 @@ static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG, TargetMachine &TM) {
   
   // If this is the first return lowered for this function, add the regs to the
   // liveout set for the function.
-  if (DAG.getMachineFunction().liveout_empty()) {
+  if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
     for (unsigned i = 0; i != RVLocs.size(); ++i)
-      DAG.getMachineFunction().addLiveOut(RVLocs[i].getLocReg());
+      DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
   }
 
   SDOperand Chain = Op.getOperand(0);
diff --git a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
index 84ff7edf195..3c8bc9f73ee 100644
--- a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
@@ -26,6 +26,7 @@
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/MachineFrameInfo.h"
 #include "llvm/CodeGen/MachineLocation.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/CodeGen/SelectionDAGNodes.h"
 #include "llvm/Target/TargetFrameInfo.h"
 #include "llvm/Target/TargetInstrInfo.h"
@@ -911,19 +912,21 @@ static void HandleVRSaveUpdate(MachineInstr *MI, const TargetInstrInfo &TII) {
 
   unsigned UsedRegMask = 0;
   for (unsigned i = 0; i != 32; ++i)
-    if (MF->isPhysRegUsed(VRRegNo[i]))
+    if (MF->getRegInfo().isPhysRegUsed(VRRegNo[i]))
       UsedRegMask |= 1 << (31-i);
   
   // Live in and live out values already must be in the mask, so don't bother
   // marking them.
-  for (MachineFunction::livein_iterator I = 
-       MF->livein_begin(), E = MF->livein_end(); I != E; ++I) {
+  for (MachineRegisterInfo::livein_iterator
+       I = MF->getRegInfo().livein_begin(),
+       E = MF->getRegInfo().livein_end(); I != E; ++I) {
     unsigned RegNo = PPCRegisterInfo::getRegisterNumbering(I->first);
     if (VRRegNo[RegNo] == I->first)        // If this really is a vector reg.
       UsedRegMask &= ~(1 << (31-RegNo));   // Doesn't need to be marked.
   }
-  for (MachineFunction::liveout_iterator I = 
-       MF->liveout_begin(), E = MF->liveout_end(); I != E; ++I) {
+  for (MachineRegisterInfo::liveout_iterator
+       I = MF->getRegInfo().liveout_begin(),
+       E = MF->getRegInfo().liveout_end(); I != E; ++I) {
     unsigned RegNo = PPCRegisterInfo::getRegisterNumbering(*I);
     if (VRRegNo[RegNo] == *I)              // If this really is a vector reg.
       UsedRegMask &= ~(1 << (31-RegNo));   // Doesn't need to be marked.
@@ -1012,8 +1015,8 @@ void PPCRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
   //  Save and clear the LR state.
   PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
   unsigned LR = getRARegister();
-  FI->setUsesLR(MF.isPhysRegUsed(LR));
-  MF.setPhysRegUnused(LR);
+  FI->setUsesLR(MF.getRegInfo().isPhysRegUsed(LR));
+  MF.getRegInfo().setPhysRegUnused(LR);
 
   //  Save R31 if necessary
   int FPSI = FI->getFramePointerSaveIndex();
@@ -1023,8 +1026,8 @@ void PPCRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
   const MachineFrameInfo *MFI = MF.getFrameInfo();
  
   // If the frame pointer save index hasn't been defined yet.
-  if (!FPSI &&  (NoFramePointerElim || MFI->hasVarSizedObjects()) 
-                                                  && IsELF32_ABI) {
+  if (!FPSI && (NoFramePointerElim || MFI->hasVarSizedObjects()) &&
+      IsELF32_ABI) {
     // Find out what the fix offset of the frame pointer save area.
     int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64,
                                                            IsMachoABI);
diff --git a/llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp b/llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp
index 040bcd54329..df63f20d85f 100644
--- a/llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp
+++ b/llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp
@@ -19,9 +19,9 @@
 #include "llvm/CodeGen/MachineFrameInfo.h"
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/CodeGen/SelectionDAG.h"
 #include "llvm/CodeGen/SelectionDAGISel.h"
-#include "llvm/CodeGen/SSARegMap.h"
 #include "llvm/Target/TargetLowering.h"
 #include "llvm/Support/Debug.h"
 #include <queue>
@@ -298,7 +298,7 @@ void SparcTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
 std::vector<SDOperand>
 SparcTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
   MachineFunction &MF = DAG.getMachineFunction();
-  SSARegMap *RegMap = MF.getSSARegMap();
+  MachineRegisterInfo &RegInfo = MF.getRegInfo();
   std::vector<SDOperand> ArgValues;
   
   static const unsigned ArgRegs[] = {
@@ -324,8 +324,8 @@ SparcTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
         if (CurArgReg < ArgRegEnd) ++CurArgReg;
         ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT));
       } else if (CurArgReg < ArgRegEnd) {  // Lives in an incoming GPR
-        unsigned VReg = RegMap->createVirtualRegister(&SP::IntRegsRegClass);
-        MF.addLiveIn(*CurArgReg++, VReg);
+        unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
+        MF.getRegInfo().addLiveIn(*CurArgReg++, VReg);
         SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32);
         if (ObjectVT != MVT::i32) {
           unsigned AssertOp = ISD::AssertSext;
@@ -362,8 +362,8 @@ SparcTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
         ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT));
       } else if (CurArgReg < ArgRegEnd) {  // Lives in an incoming GPR
         // FP value is passed in an integer register.
-        unsigned VReg = RegMap->createVirtualRegister(&SP::IntRegsRegClass);
-        MF.addLiveIn(*CurArgReg++, VReg);
+        unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
+        MF.getRegInfo().addLiveIn(*CurArgReg++, VReg);
         SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32);
 
         Arg = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Arg);
@@ -396,8 +396,8 @@ SparcTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
       } else {
         SDOperand HiVal;
         if (CurArgReg < ArgRegEnd) {  // Lives in an incoming GPR
-          unsigned VRegHi = RegMap->createVirtualRegister(&SP::IntRegsRegClass);
-          MF.addLiveIn(*CurArgReg++, VRegHi);
+          unsigned VRegHi = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
+          MF.getRegInfo().addLiveIn(*CurArgReg++, VRegHi);
           HiVal = DAG.getCopyFromReg(Root, VRegHi, MVT::i32);
         } else {
           int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
@@ -407,8 +407,8 @@ SparcTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
         
         SDOperand LoVal;
         if (CurArgReg < ArgRegEnd) {  // Lives in an incoming GPR
-          unsigned VRegLo = RegMap->createVirtualRegister(&SP::IntRegsRegClass);
-          MF.addLiveIn(*CurArgReg++, VRegLo);
+          unsigned VRegLo = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
+          MF.getRegInfo().addLiveIn(*CurArgReg++, VRegLo);
           LoVal = DAG.getCopyFromReg(Root, VRegLo, MVT::i32);
         } else {
           int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset+4);
@@ -437,8 +437,8 @@ SparcTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
     VarArgsFrameOffset = ArgOffset;
     
     for (; CurArgReg != ArgRegEnd; ++CurArgReg) {
-      unsigned VReg = RegMap->createVirtualRegister(&SP::IntRegsRegClass);
-      MF.addLiveIn(*CurArgReg, VReg);
+      unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
+      MF.getRegInfo().addLiveIn(*CurArgReg, VReg);
       SDOperand Arg = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32);
 
       int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
@@ -461,17 +461,17 @@ SparcTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
   case MVT::i8:
   case MVT::i16:
   case MVT::i32:
-    MF.addLiveOut(SP::I0);
+    MF.getRegInfo().addLiveOut(SP::I0);
     break;
   case MVT::i64:
-    MF.addLiveOut(SP::I0);
-    MF.addLiveOut(SP::I1);
+    MF.getRegInfo().addLiveOut(SP::I0);
+    MF.getRegInfo().addLiveOut(SP::I1);
     break;
   case MVT::f32:
-    MF.addLiveOut(SP::F0);
+    MF.getRegInfo().addLiveOut(SP::F0);
     break;
   case MVT::f64:
-    MF.addLiveOut(SP::D0);
+    MF.getRegInfo().addLiveOut(SP::D0);
     break;
   }
   
diff --git a/llvm/lib/Target/X86/X86FloatingPoint.cpp b/llvm/lib/Target/X86/X86FloatingPoint.cpp
index f36b80da116..354804ce5c1 100644
--- a/llvm/lib/Target/X86/X86FloatingPoint.cpp
+++ b/llvm/lib/Target/X86/X86FloatingPoint.cpp
@@ -33,6 +33,7 @@
 #include "X86InstrInfo.h"
 #include "llvm/CodeGen/MachineFunctionPass.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/CodeGen/LiveVariables.h"
 #include "llvm/CodeGen/Passes.h"
 #include "llvm/Target/TargetInstrInfo.h"
@@ -169,7 +170,7 @@ bool FPS::runOnMachineFunction(MachineFunction &MF) {
 
   assert(X86::FP6 == X86::FP0+6 && "Register enums aren't sorted right!");
   for (unsigned i = 0; i <= 6; ++i)
-    if (MF.isPhysRegUsed(X86::FP0+i)) {
+    if (MF.getRegInfo().isPhysRegUsed(X86::FP0+i)) {
       FPIsUsed = true;
       break;
     }
diff --git a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
index fa343238284..8c5cd48e091 100644
--- a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
@@ -28,7 +28,7 @@
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/MachineFrameInfo.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
-#include "llvm/CodeGen/SSARegMap.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/CodeGen/SelectionDAGISel.h"
 #include "llvm/Target/TargetMachine.h"
 #include "llvm/Support/Compiler.h"
@@ -504,7 +504,7 @@ void X86DAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
         for (unsigned op = 0, e = I->getNumOperands(); op != e; ++op) {
           if (I->getOperand(op).isRegister() && I->getOperand(op).isDef() &&
               MRegisterInfo::isVirtualRegister(I->getOperand(op).getReg()) &&
-              ((clas = RegMap->getRegClass(I->getOperand(0).getReg())) == 
+              ((clas = RegInfo->getRegClass(I->getOperand(0).getReg())) == 
                  X86::RFP32RegisterClass ||
                clas == X86::RFP64RegisterClass ||
                clas == X86::RFP80RegisterClass)) {
@@ -990,8 +990,8 @@ SDNode *X86DAGToDAGISel::getGlobalBaseReg() {
     // Insert the set of GlobalBaseReg into the first MBB of the function
     MachineBasicBlock &FirstMBB = BB->getParent()->front();
     MachineBasicBlock::iterator MBBI = FirstMBB.begin();
-    SSARegMap *RegMap = BB->getParent()->getSSARegMap();
-    unsigned PC = RegMap->createVirtualRegister(X86::GR32RegisterClass);
+    MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
+    unsigned PC = RegInfo.createVirtualRegister(X86::GR32RegisterClass);
     
     const TargetInstrInfo *TII = TM.getInstrInfo();
     // Operand of MovePCtoStack is completely ignored by asm printer. It's
@@ -1003,7 +1003,7 @@ SDNode *X86DAGToDAGISel::getGlobalBaseReg() {
     // not to pc, but to _GLOBAL_ADDRESS_TABLE_ external
     if (TM.getRelocationModel() == Reloc::PIC_ &&
         Subtarget->isPICStyleGOT()) {
-      GlobalBaseReg = RegMap->createVirtualRegister(X86::GR32RegisterClass);
+      GlobalBaseReg = RegInfo.createVirtualRegister(X86::GR32RegisterClass);
       BuildMI(FirstMBB, MBBI, TII->get(X86::ADD32ri), GlobalBaseReg).
         addReg(PC).
         addExternalSymbol("_GLOBAL_OFFSET_TABLE_");
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 4d17f55a950..a4e69c54c47 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -30,8 +30,8 @@
 #include "llvm/CodeGen/MachineFrameInfo.h"
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/CodeGen/SelectionDAG.h"
-#include "llvm/CodeGen/SSARegMap.h"
 #include "llvm/Support/MathExtras.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Target/TargetOptions.h"
@@ -703,10 +703,10 @@ SDOperand X86TargetLowering::LowerRET(SDOperand Op, SelectionDAG &DAG) {
     
   // If this is the first return lowered for this function, add the regs to the
   // liveout set for the function.
-  if (DAG.getMachineFunction().liveout_empty()) {
+  if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
     for (unsigned i = 0; i != RVLocs.size(); ++i)
       if (RVLocs[i].isRegLoc())
-        DAG.getMachineFunction().addLiveOut(RVLocs[i].getLocReg());
+        DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
   }
   SDOperand Chain = Op.getOperand(0);
   
@@ -933,8 +933,8 @@ LowerCallResult(SDOperand Chain, SDOperand InFlag, SDNode *TheCall,
 static unsigned AddLiveIn(MachineFunction &MF, unsigned PReg,
                           const TargetRegisterClass *RC) {
   assert(RC->contains(PReg) && "Not the correct regclass!");
-  unsigned VReg = MF.getSSARegMap()->createVirtualRegister(RC);
-  MF.addLiveIn(PReg, VReg);
+  unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
+  MF.getRegInfo().addLiveIn(PReg, VReg);
   return VReg;
 }
 
@@ -1754,7 +1754,7 @@ SDOperand X86TargetLowering::LowerX86_TailCallTo(SDOperand Op,
                              Callee,InFlag);
     Callee = DAG.getRegister(Opc, getPointerTy());
     // Add register as live out.
-    DAG.getMachineFunction().addLiveOut(Opc);
+    DAG.getMachineFunction().getRegInfo().addLiveOut(Opc);
   }
    
   SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
@@ -5288,7 +5288,7 @@ SDOperand X86TargetLowering::LowerEH_RETURN(SDOperand Op, SelectionDAG &DAG)
   StoreAddr = DAG.getNode(ISD::ADD, getPointerTy(), StoreAddr, Offset);
   Chain = DAG.getStore(Chain, Handler, StoreAddr, NULL, 0);
   Chain = DAG.getCopyToReg(Chain, X86::ECX, StoreAddr);
-  MF.addLiveOut(X86::ECX);
+  MF.getRegInfo().addLiveOut(X86::ECX);
 
   return DAG.getNode(X86ISD::EH_RETURN, MVT::Other,
                      Chain, DAG.getRegister(X86::ECX, getPointerTy()));
@@ -5802,7 +5802,7 @@ X86TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
 
     // Load the old value of the high byte of the control word...
     unsigned OldCW =
-      F->getSSARegMap()->createVirtualRegister(X86::GR16RegisterClass);
+      F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass);
     addFrameReference(BuildMI(BB, TII->get(X86::MOV16rm), OldCW), CWFrameIdx);
 
     // Set the high part to be round to zero...
diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp
index 3403f1c4d0c..3470baa4933 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.cpp
+++ b/llvm/lib/Target/X86/X86InstrInfo.cpp
@@ -19,8 +19,8 @@
 #include "X86TargetMachine.h"
 #include "llvm/ADT/STLExtras.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/CodeGen/LiveVariables.h"
-#include "llvm/CodeGen/SSARegMap.h"
 #include "llvm/Target/TargetOptions.h"
 using namespace llvm;
 
@@ -316,11 +316,11 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
     
     if (DisableLEA16) {
       // If 16-bit LEA is disabled, use 32-bit LEA via subregisters.
-      SSARegMap *RegMap = MFI->getParent()->getSSARegMap();
+      MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo();
       unsigned Opc = TM.getSubtarget<X86Subtarget>().is64Bit()
         ? X86::LEA64_32r : X86::LEA32r;
-      unsigned leaInReg = RegMap->createVirtualRegister(&X86::GR32RegClass);
-      unsigned leaOutReg = RegMap->createVirtualRegister(&X86::GR32RegClass);
+      unsigned leaInReg = RegInfo.createVirtualRegister(&X86::GR32RegClass);
+      unsigned leaOutReg = RegInfo.createVirtualRegister(&X86::GR32RegClass);
             
       MachineInstr *Ins =
         BuildMI(get(X86::INSERT_SUBREG), leaInReg).addReg(Src).addImm(2);
diff --git a/llvm/lib/Target/X86/X86RegisterInfo.cpp b/llvm/lib/Target/X86/X86RegisterInfo.cpp
index 07c25914a23..788bcc6c4a5 100644
--- a/llvm/lib/Target/X86/X86RegisterInfo.cpp
+++ b/llvm/lib/Target/X86/X86RegisterInfo.cpp
@@ -26,7 +26,8 @@
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/MachineFrameInfo.h"
 #include "llvm/CodeGen/MachineLocation.h"
-#include "llvm/CodeGen/SSARegMap.h"
+#include "llvm/CodeGen/MachineModuleInfo.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/Target/TargetAsmInfo.h"
 #include "llvm/Target/TargetFrameInfo.h"
 #include "llvm/Target/TargetInstrInfo.h"
@@ -1843,8 +1844,9 @@ void X86RegisterInfo::emitPrologue(MachineFunction &MF) const {
     if (NumBytes >= 4096 && Subtarget->isTargetCygMing()) {
       // Check, whether EAX is livein for this function
       bool isEAXAlive = false;
-      for (MachineFunction::livein_iterator II = MF.livein_begin(),
-             EE = MF.livein_end(); (II != EE) && !isEAXAlive; ++II) {
+      for (MachineRegisterInfo::livein_iterator
+           II = MF.getRegInfo().livein_begin(),
+           EE = MF.getRegInfo().livein_end(); (II != EE) && !isEAXAlive; ++II) {
         unsigned Reg = II->first;
         isEAXAlive = (Reg == X86::EAX || Reg == X86::AX ||
                       Reg == X86::AH || Reg == X86::AL);
@@ -1904,7 +1906,8 @@ void X86RegisterInfo::emitPrologue(MachineFunction &MF) const {
         Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
       } else {
         MachineLocation SPDst(MachineLocation::VirtualFP);
-        MachineLocation SPSrc(MachineLocation::VirtualFP, -StackSize+stackGrowth);
+        MachineLocation SPSrc(MachineLocation::VirtualFP,
+                              -StackSize+stackGrowth);
         Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
       }
     } else {