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| author | Dinar Temirbulatov <dtemirbulatov@gmail.com> | 2017-08-03 08:50:18 +0000 |
|---|---|---|
| committer | Dinar Temirbulatov <dtemirbulatov@gmail.com> | 2017-08-03 08:50:18 +0000 |
| commit | a0beedef1c9b677748a0a7f32a05690f9980f164 (patch) | |
| tree | 5cec297b407059f0c85e917ff580e4ba30bb033f /llvm/lib/Target | |
| parent | 2cb3653404f7ae095a6a5c05fa72513be7b078b5 (diff) | |
| download | bcm5719-llvm-a0beedef1c9b677748a0a7f32a05690f9980f164.tar.gz bcm5719-llvm-a0beedef1c9b677748a0a7f32a05690f9980f164.zip | |
[X86] SET0 to use XMM registers where possible PR26018 PR32862
Differential Revision: https://reviews.llvm.org/D35965
llvm-svn: 309926
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrInfo.cpp | 21 |
1 files changed, 13 insertions, 8 deletions
diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp index 09f63ecfe71..3a4876a9fc1 100644 --- a/llvm/lib/Target/X86/X86InstrInfo.cpp +++ b/llvm/lib/Target/X86/X86InstrInfo.cpp @@ -7723,7 +7723,8 @@ bool X86InstrInfo::expandPostRAPseudo(MachineInstr &MI) const { return Expand2AddrUndef(MIB, get(HasVLX ? X86::VPXORDZ128rr : X86::VXORPSrr)); // Extended register without VLX. Use a larger XOR. - SrcReg = TRI->getMatchingSuperReg(SrcReg, X86::sub_xmm, &X86::VR512RegClass); + SrcReg = + TRI->getMatchingSuperReg(SrcReg, X86::sub_xmm, &X86::VR512RegClass); MIB->getOperand(0).setReg(SrcReg); return Expand2AddrUndef(MIB, get(X86::VPXORDZrr)); } @@ -7731,20 +7732,24 @@ bool X86InstrInfo::expandPostRAPseudo(MachineInstr &MI) const { bool HasVLX = Subtarget.hasVLX(); unsigned SrcReg = MIB->getOperand(0).getReg(); const TargetRegisterInfo *TRI = &getRegisterInfo(); - if (HasVLX) - return Expand2AddrUndef(MIB, get(X86::VPXORDZ256rr)); + if (HasVLX || TRI->getEncodingValue(SrcReg) < 16) { + unsigned XReg = TRI->getSubReg(SrcReg, X86::sub_xmm); + MIB->getOperand(0).setReg(XReg); + return Expand2AddrUndef(MIB, + get(HasVLX ? X86::VPXORDZ128rr : X86::VXORPSrr)); + } + return Expand2AddrUndef(MIB, get(X86::VPXORDZrr)); + } + case X86::AVX512_512_SET0: { + const TargetRegisterInfo *TRI = &getRegisterInfo(); + unsigned SrcReg = MIB->getOperand(0).getReg(); if (TRI->getEncodingValue(SrcReg) < 16) { unsigned XReg = TRI->getSubReg(SrcReg, X86::sub_xmm); MIB->getOperand(0).setReg(XReg); return Expand2AddrUndef(MIB, get(X86::VXORPSrr)); } - // Extended register without VLX. Use a larger XOR. - SrcReg = TRI->getMatchingSuperReg(SrcReg, X86::sub_ymm, &X86::VR512RegClass); - MIB->getOperand(0).setReg(SrcReg); return Expand2AddrUndef(MIB, get(X86::VPXORDZrr)); } - case X86::AVX512_512_SET0: - return Expand2AddrUndef(MIB, get(X86::VPXORDZrr)); case X86::V_SETALLONES: return Expand2AddrUndef(MIB, get(HasAVX ? X86::VPCMPEQDrr : X86::PCMPEQDrr)); case X86::AVX2_SETALLONES: |
