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authorChris Lattner <sabre@nondot.org>2005-01-19 03:36:14 +0000
committerChris Lattner <sabre@nondot.org>2005-01-19 03:36:14 +0000
commita05cd83d2f8367d5bf0bdc8f0db64aef57e16f81 (patch)
tree0a2bb5487eadcb51df8251ffd5c85d9bb55e0ad0 /llvm/lib/Target
parent9aa48862839af8f79dbade1631589f723a2044c7 (diff)
downloadbcm5719-llvm-a05cd83d2f8367d5bf0bdc8f0db64aef57e16f81.tar.gz
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Add a hook to find out how the target handles shift amounts that are out of
range. Either they are undefined (the default), they mask the shift amount to the size of the register (X86, Alpha, etc), or they extend the shift (PPC). This defaults to undefined, which is conservatively correct. llvm-svn: 19677
Diffstat (limited to 'llvm/lib/Target')
-rw-r--r--llvm/lib/Target/TargetLowering.cpp1
1 files changed, 1 insertions, 0 deletions
diff --git a/llvm/lib/Target/TargetLowering.cpp b/llvm/lib/Target/TargetLowering.cpp
index dd8c084a597..206a8065749 100644
--- a/llvm/lib/Target/TargetLowering.cpp
+++ b/llvm/lib/Target/TargetLowering.cpp
@@ -25,6 +25,7 @@ TargetLowering::TargetLowering(TargetMachine &tm)
IsLittleEndian = TD.isLittleEndian();
ShiftAmountTy = SetCCResultTy = PointerTy = getValueType(TD.getIntPtrType());
+ ShiftAmtHandling = Undefined;
memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*));
}
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