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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2019-05-02 12:18:24 +0000 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2019-05-02 12:18:24 +0000 |
| commit | 9fa56f7829aa5f5cca911c400bb43d854b46dc15 (patch) | |
| tree | e8ac68c4000baa6de932c6a08412f6b438f80ec1 /llvm/lib/Target | |
| parent | e4a89a1beefe667691a906c8f1b4b3c343c4e9d3 (diff) | |
| download | bcm5719-llvm-9fa56f7829aa5f5cca911c400bb43d854b46dc15.tar.gz bcm5719-llvm-9fa56f7829aa5f5cca911c400bb43d854b46dc15.zip | |
[X86][SSE] Move shouldUseHorizontalOp inside isHorizontalBinOp. NFCI.
Matches what we do for lowerAddSubToHorizontalOp and will make it easier to peek through subvectors to help fix PR39921
llvm-svn: 359782
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 28 |
1 files changed, 15 insertions, 13 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index aed2c0745af..660f81b831c 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -39344,7 +39344,9 @@ static SDValue combineStore(SDNode *N, SelectionDAG &DAG, /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form /// A horizontal-op B, for some already available A and B, and if so then LHS is /// set to A, RHS to B, and the routine returns 'true'. -static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) { +static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, SelectionDAG &DAG, + const X86Subtarget &Subtarget, + bool IsCommutative) { // If either operand is undef, bail out. The binop should be simplified. if (LHS.isUndef() || RHS.isUndef()) return false; @@ -39465,6 +39467,12 @@ static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) { LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it. RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it. + + if (!shouldUseHorizontalOp(LHS == RHS, DAG, Subtarget)) + return false; + + LHS = DAG.getBitcast(VT, LHS); + RHS = DAG.getBitcast(VT, RHS); return true; } @@ -39481,10 +39489,8 @@ static SDValue combineFaddFsub(SDNode *N, SelectionDAG &DAG, // Try to synthesize horizontal add/sub from adds/subs of shuffles. if (((Subtarget.hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) || (Subtarget.hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) && - isHorizontalBinOp(LHS, RHS, IsFadd) && - shouldUseHorizontalOp(LHS == RHS, DAG, Subtarget)) - return DAG.getNode(HorizOpcode, SDLoc(N), VT, DAG.getBitcast(VT, LHS), - DAG.getBitcast(VT, RHS)); + isHorizontalBinOp(LHS, RHS, DAG, Subtarget, IsFadd)) + return DAG.getNode(HorizOpcode, SDLoc(N), VT, LHS, RHS); return SDValue(); } @@ -42380,14 +42386,12 @@ static SDValue combineAdd(SDNode *N, SelectionDAG &DAG, // Try to synthesize horizontal adds from adds of shuffles. if ((VT == MVT::v8i16 || VT == MVT::v4i32 || VT == MVT::v16i16 || VT == MVT::v8i32) && - Subtarget.hasSSSE3() && isHorizontalBinOp(Op0, Op1, true) && - shouldUseHorizontalOp(Op0 == Op1, DAG, Subtarget)) { + Subtarget.hasSSSE3() && + isHorizontalBinOp(Op0, Op1, DAG, Subtarget, true)) { auto HADDBuilder = [](SelectionDAG &DAG, const SDLoc &DL, ArrayRef<SDValue> Ops) { return DAG.getNode(X86ISD::HADD, DL, Ops[0].getValueType(), Ops); }; - Op0 = DAG.getBitcast(VT, Op0); - Op1 = DAG.getBitcast(VT, Op1); return SplitOpsAndApply(DAG, Subtarget, SDLoc(N), VT, {Op0, Op1}, HADDBuilder); } @@ -42513,14 +42517,12 @@ static SDValue combineSub(SDNode *N, SelectionDAG &DAG, EVT VT = N->getValueType(0); if ((VT == MVT::v8i16 || VT == MVT::v4i32 || VT == MVT::v16i16 || VT == MVT::v8i32) && - Subtarget.hasSSSE3() && isHorizontalBinOp(Op0, Op1, false) && - shouldUseHorizontalOp(Op0 == Op1, DAG, Subtarget)) { + Subtarget.hasSSSE3() && + isHorizontalBinOp(Op0, Op1, DAG, Subtarget, false)) { auto HSUBBuilder = [](SelectionDAG &DAG, const SDLoc &DL, ArrayRef<SDValue> Ops) { return DAG.getNode(X86ISD::HSUB, DL, Ops[0].getValueType(), Ops); }; - Op0 = DAG.getBitcast(VT, Op0); - Op1 = DAG.getBitcast(VT, Op1); return SplitOpsAndApply(DAG, Subtarget, SDLoc(N), VT, {Op0, Op1}, HSUBBuilder); } |

