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authorSimon Pilgrim <llvm-dev@redking.me.uk>2016-07-02 20:20:12 +0000
committerSimon Pilgrim <llvm-dev@redking.me.uk>2016-07-02 20:20:12 +0000
commit99e8a1aa0b1781035ba3c4975ba2066a8dbdfeca (patch)
tree7f0ac5f0a1bff6b57f2eb9a3cb4aaab8938206ac /llvm/lib/Target
parent7d5405069d4c40223405f56bf1c0e1460ddb573b (diff)
downloadbcm5719-llvm-99e8a1aa0b1781035ba3c4975ba2066a8dbdfeca.tar.gz
bcm5719-llvm-99e8a1aa0b1781035ba3c4975ba2066a8dbdfeca.zip
[X86][AVX512] Add support for lowering shuffles to VPERMILPD
llvm-svn: 274450
Diffstat (limited to 'llvm/lib/Target')
-rw-r--r--llvm/lib/Target/X86/X86ISelLowering.cpp11
1 files changed, 11 insertions, 0 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 02f92080431..f5557d340f6 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -11721,6 +11721,17 @@ static SDValue lowerV8F64VectorShuffle(const SDLoc &DL, ArrayRef<int> Mask,
// Use low duplicate instructions for masks that match their pattern.
if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2, 4, 4, 6, 6}))
return DAG.getNode(X86ISD::MOVDDUP, DL, MVT::v8f64, V1);
+
+ if (!is128BitLaneCrossingShuffleMask(MVT::v8f64, Mask)) {
+ // Non-half-crossing single input shuffles can be lowered with an
+ // interleaved permutation.
+ unsigned VPERMILPMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1) |
+ ((Mask[2] == 3) << 2) | ((Mask[3] == 3) << 3) |
+ ((Mask[4] == 5) << 4) | ((Mask[5] == 5) << 5) |
+ ((Mask[6] == 7) << 6) | ((Mask[7] == 7) << 7);
+ return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v8f64, V1,
+ DAG.getConstant(VPERMILPMask, DL, MVT::i8));
+ }
}
if (SDValue Shuf128 =
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