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| author | Evan Cheng <evan.cheng@apple.com> | 2010-10-29 23:16:55 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2010-10-29 23:16:55 +0000 |
| commit | 99cce36cf573700c2ed525e40cb4e7b9943b1bce (patch) | |
| tree | 8f3bf20d499f45f5b764104fae4fd4b4bcdf0fc5 /llvm/lib/Target | |
| parent | 7d3dfc0622341be00cf9b0c2ad79db93fa533068 (diff) | |
| download | bcm5719-llvm-99cce36cf573700c2ed525e40cb4e7b9943b1bce.tar.gz bcm5719-llvm-99cce36cf573700c2ed525e40cb4e7b9943b1bce.zip | |
Fix fpscr <-> GPR latency info.
llvm-svn: 117737
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp | 11 | ||||
| -rw-r--r-- | llvm/lib/Target/ARM/ARMScheduleA8.td | 2 | ||||
| -rw-r--r-- | llvm/lib/Target/ARM/ARMScheduleA9.td | 3 |
3 files changed, 12 insertions, 4 deletions
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp index c23bc93925b..d4b832e7bc6 100644 --- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp +++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp @@ -1914,9 +1914,16 @@ ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData, const TargetInstrDesc &UseTID = UseMI->getDesc(); const MachineOperand &DefMO = DefMI->getOperand(DefIdx); - if (DefMO.getReg() == ARM::CPSR && UseTID.isBranch()) + if (DefMO.getReg() == ARM::CPSR) { + if (DefMI->getOpcode() == ARM::FMSTAT) { + // fpscr -> cpsr stalls over 20 cycles on A8 (and earlier?) + return Subtarget.isCortexA9() ? 1 : 20; + } + // CPSR set and branch can be paired in the same cycle. - return 0; + if (UseTID.isBranch()) + return 0; + } unsigned DefAlign = DefMI->hasOneMemOperand() ? (*DefMI->memoperands_begin())->getAlignment() : 0; diff --git a/llvm/lib/Target/ARM/ARMScheduleA8.td b/llvm/lib/Target/ARM/ARMScheduleA8.td index 32d9d66837b..1f19b21e1c3 100644 --- a/llvm/lib/Target/ARM/ARMScheduleA8.td +++ b/llvm/lib/Target/ARM/ARMScheduleA8.td @@ -237,7 +237,7 @@ def CortexA8Itineraries : ProcessorItineraries< // // FP Special Register to Integer Register File Move InstrItinData<IIC_fpSTAT , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, - InstrStage<1, [A8_NLSPipe]>]>, + InstrStage<1, [A8_NLSPipe]>], [20]>, // // Single-precision FP Unary InstrItinData<IIC_fpUNA32 , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, diff --git a/llvm/lib/Target/ARM/ARMScheduleA9.td b/llvm/lib/Target/ARM/ARMScheduleA9.td index 20aa64163bf..3096b0ad990 100644 --- a/llvm/lib/Target/ARM/ARMScheduleA9.td +++ b/llvm/lib/Target/ARM/ARMScheduleA9.td @@ -431,7 +431,8 @@ def CortexA9Itineraries : ProcessorItineraries< InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsVFP], 0, Required>, InstrStage<2, [A9_DRegsN], 0, Reserved>, - InstrStage<1, [A9_NPipe]>]>, + InstrStage<1, [A9_NPipe]>], + [1]>, // // Single-precision FP Unary InstrItinData<IIC_fpUNA32 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, |
