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author | Joerg Sonnenberger <joerg@bec.de> | 2014-08-02 15:09:41 +0000 |
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committer | Joerg Sonnenberger <joerg@bec.de> | 2014-08-02 15:09:41 +0000 |
commit | 99ab590ac990e41f390e3be2351e2348f8c6b7df (patch) | |
tree | ea222e4ecb82cf531e6d573d48de3471b50aeed1 /llvm/lib/Target | |
parent | 466a31eb65339bcd4212ec7b31ceebfd8a4a2b4f (diff) | |
download | bcm5719-llvm-99ab590ac990e41f390e3be2351e2348f8c6b7df.tar.gz bcm5719-llvm-99ab590ac990e41f390e3be2351e2348f8c6b7df.zip |
Don't use additional arguments for dss and friends to satisfy DSS_Form,
when let can do the same thing. Keep the 64bit variants as codegen-only.
While they have a different register class, the encoding is the same for
32bit and 64bit mode. Having both present would otherwise confuse the
disassembler.
llvm-svn: 214636
Diffstat (limited to 'llvm/lib/Target')
-rw-r--r-- | llvm/lib/Target/PowerPC/PPCInstrAltivec.td | 114 | ||||
-rw-r--r-- | llvm/lib/Target/PowerPC/PPCInstrFormats.td | 3 |
2 files changed, 54 insertions, 63 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCInstrAltivec.td b/llvm/lib/Target/PowerPC/PPCInstrAltivec.td index 0924cd8bb1b..33d3a7e4715 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrAltivec.td +++ b/llvm/lib/Target/PowerPC/PPCInstrAltivec.td @@ -258,48 +258,64 @@ class VX2_Int_Ty2<bits<11> xo, string opc, Intrinsic IntID, ValueType OutTy, def HasAltivec : Predicate<"PPCSubTarget->hasAltivec()">; let Predicates = [HasAltivec] in { -let isCodeGenOnly = 1 in { -def DSS : DSS_Form<822, (outs), - (ins u5imm:$ZERO0, u5imm:$STRM,u5imm:$ZERO1,u5imm:$ZERO2), - "dss $STRM", IIC_LdStLoad /*FIXME*/, []>, - Deprecated<DeprecatedDST>; -def DSSALL : DSS_Form<822, (outs), - (ins u5imm:$ONE, u5imm:$ZERO0,u5imm:$ZERO1,u5imm:$ZERO2), - "dssall", IIC_LdStLoad /*FIXME*/, []>, - Deprecated<DeprecatedDST>; -def DST : DSS_Form<342, (outs), - (ins u5imm:$ZERO, u5imm:$STRM, gprc:$rA, gprc:$rB), - "dst $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, []>, - Deprecated<DeprecatedDST>; -def DSTT : DSS_Form<342, (outs), - (ins u5imm:$ONE, u5imm:$STRM, gprc:$rA, gprc:$rB), - "dstt $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, []>, - Deprecated<DeprecatedDST>; -def DSTST : DSS_Form<374, (outs), - (ins u5imm:$ZERO, u5imm:$STRM, gprc:$rA, gprc:$rB), - "dstst $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, []>, - Deprecated<DeprecatedDST>; -def DSTSTT : DSS_Form<374, (outs), - (ins u5imm:$ONE, u5imm:$STRM, gprc:$rA, gprc:$rB), - "dststt $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, []>, - Deprecated<DeprecatedDST>; +def DSS : DSS_Form<0, 822, (outs), (ins u5imm:$STRM), + "dss $STRM", IIC_LdStLoad /*FIXME*/, [(int_ppc_altivec_dss imm:$STRM)]>, + Deprecated<DeprecatedDST> { + let A = 0; + let B = 0; +} -def DST64 : DSS_Form<342, (outs), - (ins u5imm:$ZERO, u5imm:$STRM, g8rc:$rA, gprc:$rB), - "dst $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, []>, +def DSSALL : DSS_Form<1, 822, (outs), (ins), + "dssall", IIC_LdStLoad /*FIXME*/, [(int_ppc_altivec_dssall)]>, + Deprecated<DeprecatedDST> { + let STRM = 0; + let A = 0; + let B = 0; +} + +def DST : DSS_Form<0, 342, (outs), (ins u5imm:$STRM, gprc:$rA, gprc:$rB), + "dst $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, + [(int_ppc_altivec_dst i32:$rA, i32:$rB, imm:$STRM)]>, Deprecated<DeprecatedDST>; -def DSTT64 : DSS_Form<342, (outs), - (ins u5imm:$ONE, u5imm:$STRM, g8rc:$rA, gprc:$rB), - "dstt $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, []>, + +def DSTT : DSS_Form<1, 342, (outs), (ins u5imm:$STRM, gprc:$rA, gprc:$rB), + "dstt $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, + [(int_ppc_altivec_dstt i32:$rA, i32:$rB, imm:$STRM)]>, Deprecated<DeprecatedDST>; -def DSTST64 : DSS_Form<374, (outs), - (ins u5imm:$ZERO, u5imm:$STRM, g8rc:$rA, gprc:$rB), - "dstst $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, []>, + +def DSTST : DSS_Form<0, 374, (outs), (ins u5imm:$STRM, gprc:$rA, gprc:$rB), + "dstst $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, + [(int_ppc_altivec_dstst i32:$rA, i32:$rB, imm:$STRM)]>, Deprecated<DeprecatedDST>; -def DSTSTT64 : DSS_Form<374, (outs), - (ins u5imm:$ONE, u5imm:$STRM, g8rc:$rA, gprc:$rB), - "dststt $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, []>, + +def DSTSTT : DSS_Form<1, 374, (outs), (ins u5imm:$STRM, gprc:$rA, gprc:$rB), + "dststt $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, + [(int_ppc_altivec_dststt i32:$rA, i32:$rB, imm:$STRM)]>, Deprecated<DeprecatedDST>; + +let isCodeGenOnly = 1 in { + // The very same instructions as above, but formally matching 64bit registers. + def DST64 : DSS_Form<0, 342, (outs), (ins u5imm:$STRM, g8rc:$rA, gprc:$rB), + "dst $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, + [(int_ppc_altivec_dst i64:$rA, i32:$rB, imm:$STRM)]>, + Deprecated<DeprecatedDST>; + + def DSTT64 : DSS_Form<1, 342, (outs), (ins u5imm:$STRM, g8rc:$rA, gprc:$rB), + "dstt $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, + [(int_ppc_altivec_dstt i64:$rA, i32:$rB, imm:$STRM)]>, + Deprecated<DeprecatedDST>; + + def DSTST64 : DSS_Form<0, 374, (outs), (ins u5imm:$STRM, g8rc:$rA, gprc:$rB), + "dstst $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, + [(int_ppc_altivec_dstst i64:$rA, i32:$rB, + imm:$STRM)]>, + Deprecated<DeprecatedDST>; + + def DSTSTT64 : DSS_Form<1, 374, (outs), (ins u5imm:$STRM, g8rc:$rA, gprc:$rB), + "dststt $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, + [(int_ppc_altivec_dststt i64:$rA, i32:$rB, + imm:$STRM)]>, + Deprecated<DeprecatedDST>; } def MFVSCR : VXForm_4<1540, (outs vrrc:$vD), (ins), @@ -747,30 +763,6 @@ def V_SETALLONES : VXForm_3<908, (outs vrrc:$vD), (ins), // Additional Altivec Patterns // -// DS* intrinsics -def : Pat<(int_ppc_altivec_dssall), (DSSALL 1, 0, 0, 0)>; -def : Pat<(int_ppc_altivec_dss imm:$STRM), (DSS 0, imm:$STRM, 0, 0)>; - -// * 32-bit -def : Pat<(int_ppc_altivec_dst i32:$rA, i32:$rB, imm:$STRM), - (DST 0, imm:$STRM, $rA, $rB)>; -def : Pat<(int_ppc_altivec_dstt i32:$rA, i32:$rB, imm:$STRM), - (DSTT 1, imm:$STRM, $rA, $rB)>; -def : Pat<(int_ppc_altivec_dstst i32:$rA, i32:$rB, imm:$STRM), - (DSTST 0, imm:$STRM, $rA, $rB)>; -def : Pat<(int_ppc_altivec_dststt i32:$rA, i32:$rB, imm:$STRM), - (DSTSTT 1, imm:$STRM, $rA, $rB)>; - -// * 64-bit -def : Pat<(int_ppc_altivec_dst i64:$rA, i32:$rB, imm:$STRM), - (DST64 0, imm:$STRM, $rA, $rB)>; -def : Pat<(int_ppc_altivec_dstt i64:$rA, i32:$rB, imm:$STRM), - (DSTT64 1, imm:$STRM, $rA, $rB)>; -def : Pat<(int_ppc_altivec_dstst i64:$rA, i32:$rB, imm:$STRM), - (DSTST64 0, imm:$STRM, $rA, $rB)>; -def : Pat<(int_ppc_altivec_dststt i64:$rA, i32:$rB, imm:$STRM), - (DSTSTT64 1, imm:$STRM, $rA, $rB)>; - // Loads. def : Pat<(v4i32 (load xoaddr:$src)), (LVX xoaddr:$src)>; diff --git a/llvm/lib/Target/PowerPC/PPCInstrFormats.td b/llvm/lib/Target/PowerPC/PPCInstrFormats.td index 18d77cdd803..8a5a60b6595 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrFormats.td +++ b/llvm/lib/Target/PowerPC/PPCInstrFormats.td @@ -800,10 +800,9 @@ class DCB_Form<bits<10> xo, bits<5> immfield, dag OOL, dag IOL, string asmstr, // DSS_Form - Form X instruction, used for altivec dss* instructions. -class DSS_Form<bits<10> xo, dag OOL, dag IOL, string asmstr, +class DSS_Form<bits<1> T, bits<10> xo, dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> : I<31, OOL, IOL, asmstr, itin> { - bits<1> T; bits<2> STRM; bits<5> A; bits<5> B; |