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| author | Hal Finkel <hfinkel@anl.gov> | 2012-06-13 05:55:09 +0000 |
|---|---|---|
| committer | Hal Finkel <hfinkel@anl.gov> | 2012-06-13 05:55:09 +0000 |
| commit | 98986148541b00838db57e3e9a24c74c6e6980b9 (patch) | |
| tree | ff4b95a52a03c0eab4a34273246afc9cf2c27c4c /llvm/lib/Target | |
| parent | d33f4efbfdef6ffccf212ab3e40a7673589085fd (diff) | |
| download | bcm5719-llvm-98986148541b00838db57e3e9a24c74c6e6980b9.tar.gz bcm5719-llvm-98986148541b00838db57e3e9a24c74c6e6980b9.zip | |
Add another missing 64-bit itinerary definition for the PPC A2 core.
llvm-svn: 158393
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCScheduleA2.td | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCScheduleA2.td b/llvm/lib/Target/PowerPC/PPCScheduleA2.td index 54e945c9138..4d4a5d0e1b2 100644 --- a/llvm/lib/Target/PowerPC/PPCScheduleA2.td +++ b/llvm/lib/Target/PowerPC/PPCScheduleA2.td @@ -302,6 +302,17 @@ def PPCA2Itineraries : ProcessorItineraries< InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>], [14, 7], [GPR_Bypass, GPR_Bypass]>, + InstrItinData<LdStLD , [InstrStage<4, + [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>, + InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, + IU4_4, IU4_5, IU4_6, IU4_7]>, + InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, + InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>, + InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>, + InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>, + InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>], + [14, 7], + [GPR_Bypass, GPR_Bypass]>, InstrItinData<LdStStore , [InstrStage<4, [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>, InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, |
