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authorCraig Topper <craig.topper@gmail.com>2011-12-29 18:08:36 +0000
committerCraig Topper <craig.topper@gmail.com>2011-12-29 18:08:36 +0000
commit97f05c576853daba5cce8fb72a1640d2cb9d66d6 (patch)
tree36cd6ff48757e1a0475c0ffdda18d921e9c87279 /llvm/lib/Target
parent1559123c774a11c013cc7ef8a1e956e4c155a90e (diff)
downloadbcm5719-llvm-97f05c576853daba5cce8fb72a1640d2cb9d66d6.tar.gz
bcm5719-llvm-97f05c576853daba5cce8fb72a1640d2cb9d66d6.zip
Mark non-VEX forms of PCLMUL instructions as requiring SSE2 to be enabled along with CLMUL. That's required for the XMM registers to be valid for integer data. Doesn't change any behavior since the CLMUL instructions don't have patterns yet.
llvm-svn: 147345
Diffstat (limited to 'llvm/lib/Target')
-rw-r--r--llvm/lib/Target/X86/X86InstrFormats.td2
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/X86/X86InstrFormats.td b/llvm/lib/Target/X86/X86InstrFormats.td
index 739fa3521f9..b3a70871ced 100644
--- a/llvm/lib/Target/X86/X86InstrFormats.td
+++ b/llvm/lib/Target/X86/X86InstrFormats.td
@@ -494,7 +494,7 @@ class AESAI<bits<8> o, Format F, dag outs, dag ins, string asm,
class CLMULIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
list<dag>pattern>
: Ii8<o, F, outs, ins, asm, pattern, SSEPackedInt>, TA,
- OpSize, Requires<[HasCLMUL]>;
+ OpSize, Requires<[HasSSE2, HasCLMUL]>;
class AVXCLMULIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
list<dag>pattern>
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