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| author | Andrew Lenharth <andrewl@lenharth.org> | 2005-11-11 23:08:46 +0000 |
|---|---|---|
| committer | Andrew Lenharth <andrewl@lenharth.org> | 2005-11-11 23:08:46 +0000 |
| commit | 97e8207a059a9ee8b1c3e6cbc6bbb2da255940fb (patch) | |
| tree | 68d7617d42b8020bd6a88cd8b1b66e7349aa5817 /llvm/lib/Target | |
| parent | fab772045e5d93b3b6e2885010b0871ba14f9bb3 (diff) | |
| download | bcm5719-llvm-97e8207a059a9ee8b1c3e6cbc6bbb2da255940fb.tar.gz bcm5719-llvm-97e8207a059a9ee8b1c3e6cbc6bbb2da255940fb.zip | |
fix yet more regressions
llvm-svn: 24308
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/Alpha/AlphaISelPattern.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/Alpha/AlphaISelPattern.cpp b/llvm/lib/Target/Alpha/AlphaISelPattern.cpp index ec3479d15f5..1127f8b9e49 100644 --- a/llvm/lib/Target/Alpha/AlphaISelPattern.cpp +++ b/llvm/lib/Target/Alpha/AlphaISelPattern.cpp @@ -1530,7 +1530,7 @@ unsigned AlphaISel::SelectExpr(SDOperand N) { N.getOperand(0).getValueType() == MVT::f64 && "only f64 to f32 conversion supported here"); Tmp1 = SelectExpr(N.getOperand(0)); - BuildMI(BB, Alpha::CVTTS, 1, Result).addReg(Alpha::F31).addReg(Tmp1); + BuildMI(BB, Alpha::CVTTS, 1, Result).addReg(Tmp1); return Result; case ISD::FP_EXTEND: |
