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author | Evan Cheng <evan.cheng@apple.com> | 2007-05-16 21:20:37 +0000 |
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committer | Evan Cheng <evan.cheng@apple.com> | 2007-05-16 21:20:37 +0000 |
commit | 973c3739b07433f0fe8eca8e2da1c07cc20dbc4a (patch) | |
tree | 0033e186b0b0d0f6063af0ca6eaaf1fe001e7452 /llvm/lib/Target | |
parent | 5ea933a0097f487ff713699d5b381680cbf685ce (diff) | |
download | bcm5719-llvm-973c3739b07433f0fe8eca8e2da1c07cc20dbc4a.tar.gz bcm5719-llvm-973c3739b07433f0fe8eca8e2da1c07cc20dbc4a.zip |
Add default implementation of PredicateInstruction().
llvm-svn: 37123
Diffstat (limited to 'llvm/lib/Target')
-rw-r--r-- | llvm/lib/Target/TargetInstrInfo.cpp | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/llvm/lib/Target/TargetInstrInfo.cpp b/llvm/lib/Target/TargetInstrInfo.cpp index b9fca8a1bfd..fe5ee1d25e0 100644 --- a/llvm/lib/Target/TargetInstrInfo.cpp +++ b/llvm/lib/Target/TargetInstrInfo.cpp @@ -59,3 +59,23 @@ MachineInstr *TargetInstrInfo::commuteInstruction(MachineInstr *MI) const { MI->getOperand(1).unsetIsKill(); return MI; } + +void TargetInstrInfo::PredicateInstruction(MachineInstr *MI, + std::vector<MachineOperand> &Cond) const { + const TargetInstrDescriptor *TID = MI->getInstrDescriptor(); + assert((TID->Flags & M_PREDICABLE) && + "Predicating an unpredicable instruction!"); + + for (unsigned j = 0, i = 0, e = MI->getNumOperands(); i != e; ++i) { + if ((TID->OpInfo[i].Flags & M_PREDICATE_OPERAND)) { + MachineOperand &MO = MI->getOperand(i); + if (MO.isReg()) + MO.setReg(Cond[j].getReg()); + else if (MO.isImm()) + MO.setImm(Cond[j].getImmedValue()); + else if (MO.isMBB()) + MO.setMachineBasicBlock(Cond[j].getMachineBasicBlock()); + ++j; + } + } +} |