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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2020-01-02 20:59:29 -0500 |
|---|---|---|
| committer | Matt Arsenault <arsenm2@gmail.com> | 2020-01-03 15:25:49 -0500 |
| commit | 92ff017a857b085c8b729a744b4265b3f7a6a1d4 (patch) | |
| tree | fa1fd72d8d15c06cefa5394998f5d9a6fe8e9d11 /llvm/lib/Target | |
| parent | 5d5d5838ce07a62c1c98c8a4e82270aa927dfc10 (diff) | |
| download | bcm5719-llvm-92ff017a857b085c8b729a744b4265b3f7a6a1d4.tar.gz bcm5719-llvm-92ff017a857b085c8b729a744b4265b3f7a6a1d4.zip | |
AMDGPU: Only allow regs for s_movrel_{b32|b64}
This would incorrectly allowing folding immediates. These currently
aren't selectable, but will be from GlobalISel soon.
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SOPInstructions.td | 15 |
1 files changed, 13 insertions, 2 deletions
diff --git a/llvm/lib/Target/AMDGPU/SOPInstructions.td b/llvm/lib/Target/AMDGPU/SOPInstructions.td index ab72a582710..c7893d3be55 100644 --- a/llvm/lib/Target/AMDGPU/SOPInstructions.td +++ b/llvm/lib/Target/AMDGPU/SOPInstructions.td @@ -85,6 +85,11 @@ class SOP1_32 <string opName, list<dag> pattern=[], bit tied_in = 0> : SOP1_Pseu let Constraints = !if(tied_in, "$sdst = $sdst_in", ""); } +// Only register input allowed. +class SOP1_32R <string opName, list<dag> pattern=[]> : SOP1_Pseudo < + opName, (outs SReg_32:$sdst), (ins SReg_32:$src0), + "$sdst, $src0", pattern>; + // 32-bit input, no output. class SOP1_0_32 <string opName, list<dag> pattern = []> : SOP1_Pseudo < opName, (outs), (ins SSrc_b32:$src0), @@ -103,6 +108,12 @@ class SOP1_64 <string opName, list<dag> pattern=[]> : SOP1_Pseudo < "$sdst, $src0", pattern >; +// Only register input allowed. +class SOP1_64R <string opName, list<dag> pattern=[]> : SOP1_Pseudo < + opName, (outs SReg_64:$sdst), (ins SReg_64:$src0), + "$sdst, $src0", pattern +>; + // 64-bit input, 32-bit output. class SOP1_32_64 <string opName, list<dag> pattern=[]> : SOP1_Pseudo < opName, (outs SReg_32:$sdst), (ins SSrc_b64:$src0), @@ -254,8 +265,8 @@ def S_QUADMASK_B32 : SOP1_32 <"s_quadmask_b32">; def S_QUADMASK_B64 : SOP1_64 <"s_quadmask_b64">; let Uses = [M0] in { -def S_MOVRELS_B32 : SOP1_32 <"s_movrels_b32">; -def S_MOVRELS_B64 : SOP1_64 <"s_movrels_b64">; +def S_MOVRELS_B32 : SOP1_32R <"s_movrels_b32">; +def S_MOVRELS_B64 : SOP1_64R <"s_movrels_b64">; def S_MOVRELD_B32 : SOP1_32 <"s_movreld_b32">; def S_MOVRELD_B64 : SOP1_64 <"s_movreld_b64">; } // End Uses = [M0] |
