Replace MachineInstr* with MachineInstr& in TargetInstrInfo, NFC

There were a few cases introduced with the modulo scheduler.

llvm-svn: 277358

5 files changed, 31 insertions, 31 deletions

diff --git a/llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp b/llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp
index 2f19120f186..8fc4d955b5a 100644
--- a/llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp
@@ -670,7 +670,7 @@ void HexagonEarlyIfConversion::predicateInstr(MachineBasicBlock *ToB,
     assert(COpc);
     MachineInstrBuilder MIB = BuildMI(*ToB, At, DL, HII->get(COpc));
     MIOperands MO(*MI);
-    if (HII->isPostIncrement(MI)) {
+    if (HII->isPostIncrement(*MI)) {
       MIB.addOperand(*MO);
       ++MO;
     }
diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
index f7115dd61c3..92137ec4ad7 100644
--- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
@@ -684,18 +684,18 @@ bool HexagonInstrInfo::analyzeLoop(MachineLoop &L,
 /// finished. Return the value/register of the new loop count. this function
 /// assumes the nth iteration is peeled first.
 unsigned HexagonInstrInfo::reduceLoopCount(MachineBasicBlock &MBB,
-      MachineInstr *IndVar, MachineInstr *Cmp,
+      MachineInstr *IndVar, MachineInstr &Cmp,
       SmallVectorImpl<MachineOperand> &Cond,
       SmallVectorImpl<MachineInstr *> &PrevInsts,
       unsigned Iter, unsigned MaxIter) const {
   // We expect a hardware loop currently. This means that IndVar is set
   // to null, and the compare is the ENDLOOP instruction.
-  assert((!IndVar) && isEndLoopN(Cmp->getOpcode())
+  assert((!IndVar) && isEndLoopN(Cmp.getOpcode())
                    && "Expecting a hardware loop");
   MachineFunction *MF = MBB.getParent();
-  DebugLoc DL = Cmp->getDebugLoc();
+  DebugLoc DL = Cmp.getDebugLoc();
   SmallPtrSet<MachineBasicBlock *, 8> VisitedBBs;
-  MachineInstr *Loop = findLoopInstr(&MBB, Cmp->getOpcode(), VisitedBBs);
+  MachineInstr *Loop = findLoopInstr(&MBB, Cmp.getOpcode(), VisitedBBs);
   if (!Loop)
     return 0;
   // If the loop trip count is a compile-time value, then just change the
@@ -1346,8 +1346,8 @@ void HexagonInstrInfo::insertNoop(MachineBasicBlock &MBB,
 }
 
 
-bool HexagonInstrInfo::isPostIncrement(const MachineInstr *MI) const {
-  return getAddrMode(*MI) == HexagonII::PostInc;
+bool HexagonInstrInfo::isPostIncrement(const MachineInstr &MI) const {
+  return getAddrMode(MI) == HexagonII::PostInc;
 }
 
 
@@ -1677,14 +1677,14 @@ bool HexagonInstrInfo::areMemAccessesTriviallyDisjoint(
 
 
 /// If the instruction is an increment of a constant value, return the amount.
-bool HexagonInstrInfo::getIncrementValue(const MachineInstr *MI,
+bool HexagonInstrInfo::getIncrementValue(const MachineInstr &MI,
       int &Value) const {
   if (isPostIncrement(MI)) {
     unsigned AccessSize;
-    return getBaseAndOffset(*MI, Value, AccessSize);
+    return getBaseAndOffset(MI, Value, AccessSize);
   }
-  if (MI->getOpcode() == Hexagon::A2_addi) {
-    Value = MI->getOperand(2).getImm();
+  if (MI.getOpcode() == Hexagon::A2_addi) {
+    Value = MI.getOperand(2).getImm();
     return true;
   }
 
@@ -3160,7 +3160,7 @@ unsigned HexagonInstrInfo::getBaseAndOffset(const MachineInstr &MI,
   // Return if it is not a base+offset type instruction or a MemOp.
   if (getAddrMode(MI) != HexagonII::BaseImmOffset &&
       getAddrMode(MI) != HexagonII::BaseLongOffset &&
-      !isMemOp(MI) && !isPostIncrement(&MI))
+      !isMemOp(MI) && !isPostIncrement(MI))
     return 0;
 
   // Since it is a memory access instruction, getMemAccessSize() should never
@@ -3175,12 +3175,12 @@ unsigned HexagonInstrInfo::getBaseAndOffset(const MachineInstr &MI,
   AccessSize = (1U << (getMemAccessSize(MI) - 1));
 
   unsigned basePos = 0, offsetPos = 0;
-  if (!getBaseAndOffsetPosition(&MI, basePos, offsetPos))
+  if (!getBaseAndOffsetPosition(MI, basePos, offsetPos))
     return 0;
 
   // Post increment updates its EA after the mem access,
   // so we need to treat its offset as zero.
-  if (isPostIncrement(&MI))
+  if (isPostIncrement(MI))
     Offset = 0;
   else {
     Offset = MI.getOperand(offsetPos).getImm();
@@ -3191,22 +3191,22 @@ unsigned HexagonInstrInfo::getBaseAndOffset(const MachineInstr &MI,
 
 
 /// Return the position of the base and offset operands for this instruction.
-bool HexagonInstrInfo::getBaseAndOffsetPosition(const MachineInstr *MI,
+bool HexagonInstrInfo::getBaseAndOffsetPosition(const MachineInstr &MI,
       unsigned &BasePos, unsigned &OffsetPos) const {
   // Deal with memops first.
-  if (isMemOp(*MI)) {
+  if (isMemOp(MI)) {
     BasePos = 0;
     OffsetPos = 1;
-  } else if (MI->mayStore()) {
+  } else if (MI.mayStore()) {
     BasePos = 0;
     OffsetPos = 1;
-  } else if (MI->mayLoad()) {
+  } else if (MI.mayLoad()) {
     BasePos = 1;
     OffsetPos = 2;
   } else
     return false;
 
-  if (isPredicated(*MI)) {
+  if (isPredicated(MI)) {
     BasePos++;
     OffsetPos++;
   }
@@ -3215,7 +3215,7 @@ bool HexagonInstrInfo::getBaseAndOffsetPosition(const MachineInstr *MI,
     OffsetPos++;
   }
 
-  if (!MI->getOperand(BasePos).isReg() || !MI->getOperand(OffsetPos).isImm())
+  if (!MI.getOperand(BasePos).isReg() || !MI.getOperand(OffsetPos).isImm())
     return false;
 
   return true;
diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.h b/llvm/lib/Target/Hexagon/HexagonInstrInfo.h
index d9d0ea5961d..72f89ab8ff2 100644
--- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.h
+++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.h
@@ -114,7 +114,7 @@ public:
   /// this function when peeling off one or more iterations of a loop. This
   /// function assumes the nth iteration is peeled first.
   unsigned reduceLoopCount(MachineBasicBlock &MBB,
-                           MachineInstr *IndVar, MachineInstr *Cmp,
+                           MachineInstr *IndVar, MachineInstr &Cmp,
                            SmallVectorImpl<MachineOperand> &Cond,
                            SmallVectorImpl<MachineInstr *> &PrevInsts,
                            unsigned Iter, unsigned MaxIter) const override;
@@ -206,7 +206,7 @@ public:
   bool isPredicated(const MachineInstr &MI) const override;
 
   /// Return true for post-incremented instructions.
-  bool isPostIncrement(const MachineInstr *MI) const override;
+  bool isPostIncrement(const MachineInstr &MI) const override;
 
   /// Convert the instruction into a predicated instruction.
   /// It returns true if the operation was successful.
@@ -274,11 +274,11 @@ public:
 
   /// For instructions with a base and offset, return the position of the
   /// base register and offset operands.
-  bool getBaseAndOffsetPosition(const MachineInstr *MI, unsigned &BasePos,
+  bool getBaseAndOffsetPosition(const MachineInstr &MI, unsigned &BasePos,
                                 unsigned &OffsetPos) const override;
 
   /// If the instruction is an increment of a constant value, return the amount.
-  bool getIncrementValue(const MachineInstr *MI, int &Value) const override;
+  bool getIncrementValue(const MachineInstr &MI, int &Value) const override;
 
   /// HexagonInstrInfo specifics.
   ///
diff --git a/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp b/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp
index b01c5140a2b..9372a55f1e0 100644
--- a/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp
@@ -336,17 +336,17 @@ void HexagonSubtarget::adjustSchedDependency(SUnit *Src, SUnit *Dst,
     return;
 
   // Don't adjust the latency of post-increment part of the instruction.
-  if (QII->isPostIncrement(SrcInst) && Dep.isAssignedRegDep()) {
+  if (QII->isPostIncrement(*SrcInst) && Dep.isAssignedRegDep()) {
     if (SrcInst->mayStore())
       return;
     if (Dep.getReg() != SrcInst->getOperand(0).getReg())
       return;
-  } else if (QII->isPostIncrement(DstInst) && Dep.getKind() == SDep::Anti) {
+  } else if (QII->isPostIncrement(*DstInst) && Dep.getKind() == SDep::Anti) {
     if (DstInst->mayStore())
       return;
     if (Dep.getReg() != DstInst->getOperand(0).getReg())
       return;
-  } else if (QII->isPostIncrement(DstInst) && DstInst->mayStore() &&
+  } else if (QII->isPostIncrement(*DstInst) && DstInst->mayStore() &&
              Dep.isAssignedRegDep()) {
     MachineOperand &Op = DstInst->getOperand(DstInst->getNumOperands() - 1);
     if (Op.isReg() && Dep.getReg() != Op.getReg())
diff --git a/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp b/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
index 9802f7c69ea..32aacae89b7 100644
--- a/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
@@ -497,7 +497,7 @@ static PredicateKind getPredicateSense(const MachineInstr &MI,
 
 static const MachineOperand &getPostIncrementOperand(const MachineInstr &MI,
       const HexagonInstrInfo *HII) {
-  assert(HII->isPostIncrement(&MI) && "Not a post increment operation.");
+  assert(HII->isPostIncrement(MI) && "Not a post increment operation.");
 #ifndef NDEBUG
   // Post Increment means duplicates. Use dense map to find duplicates in the
   // list. Caution: Densemap initializes with the minimum of 64 buckets,
@@ -600,12 +600,12 @@ bool HexagonPacketizerList::canPromoteToNewValueStore(const MachineInstr &MI,
 
   // Make sure it's NOT the post increment register that we are going to
   // new value.
-  if (HII->isPostIncrement(&MI) &&
+  if (HII->isPostIncrement(MI) &&
       getPostIncrementOperand(MI, HII).getReg() == DepReg) {
     return false;
   }
 
-  if (HII->isPostIncrement(&PacketMI) && PacketMI.mayLoad() &&
+  if (HII->isPostIncrement(PacketMI) && PacketMI.mayLoad() &&
       getPostIncrementOperand(PacketMI, HII).getReg() == DepReg) {
     // If source is post_inc, or absolute-set addressing, it can not feed
     // into new value store
@@ -703,7 +703,7 @@ bool HexagonPacketizerList::canPromoteToNewValueStore(const MachineInstr &MI,
   //    The following store can not be dot new.
   //    Eg.   r0 = add(r0, #3)
   //          memw(r1+r0<<#2) = r0
-  if (!HII->isPostIncrement(&MI)) {
+  if (!HII->isPostIncrement(MI)) {
     for (unsigned opNum = 0; opNum < MI.getNumOperands()-1; opNum++) {
       const MachineOperand &MO = MI.getOperand(opNum);
       if (MO.isReg() && MO.getReg() == DepReg)