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| author | Misha Brukman <brukman+llvm@gmail.com> | 2004-08-09 19:13:29 +0000 |
|---|---|---|
| committer | Misha Brukman <brukman+llvm@gmail.com> | 2004-08-09 19:13:29 +0000 |
| commit | 8f951e579b496cfcc746755e19dfdb2d6c2b3182 (patch) | |
| tree | c55b30508c509ae9233b516d4e74afa5dd3cfca2 /llvm/lib/Target | |
| parent | 920ae9524df8f60994ff29de13f0e7d5dcd1d3e2 (diff) | |
| download | bcm5719-llvm-8f951e579b496cfcc746755e19dfdb2d6c2b3182.tar.gz bcm5719-llvm-8f951e579b496cfcc746755e19dfdb2d6c2b3182.zip | |
Remove ClassPrefix variable as it's no longer used.
llvm-svn: 15586
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/PowerPC/PowerPCInstrFormats.td | 1 | ||||
| -rw-r--r-- | llvm/lib/Target/SparcV8/SparcV8InstrInfo.td | 1 | ||||
| -rw-r--r-- | llvm/lib/Target/SparcV9/SparcV9.td | 1 | ||||
| -rw-r--r-- | llvm/lib/Target/Target.td | 1 |
4 files changed, 0 insertions, 4 deletions
diff --git a/llvm/lib/Target/PowerPC/PowerPCInstrFormats.td b/llvm/lib/Target/PowerPC/PowerPCInstrFormats.td index bec1c5d3367..7e54786f8c8 100644 --- a/llvm/lib/Target/PowerPC/PowerPCInstrFormats.td +++ b/llvm/lib/Target/PowerPC/PowerPCInstrFormats.td @@ -56,7 +56,6 @@ class PPC32I<string name, bits<6> opcode, bit ppc64, bit vmx> : Instruction { let Name = name; let Namespace = "PPC32"; - let ClassPrefix = "PowerPC"; let Inst{0-5} = opcode; } diff --git a/llvm/lib/Target/SparcV8/SparcV8InstrInfo.td b/llvm/lib/Target/SparcV8/SparcV8InstrInfo.td index 5e61d513295..07491eb1c10 100644 --- a/llvm/lib/Target/SparcV8/SparcV8InstrInfo.td +++ b/llvm/lib/Target/SparcV8/SparcV8InstrInfo.td @@ -19,7 +19,6 @@ class InstV8 : Instruction { // SparcV8 instruction baseline field bits<32> Inst; let Namespace = "V8"; - let ClassPrefix = "SparcV8"; bits<2> op; let Inst{31-30} = op; // Top two bits are the 'op' field diff --git a/llvm/lib/Target/SparcV9/SparcV9.td b/llvm/lib/Target/SparcV9/SparcV9.td index 2adc5006de7..f78317ddaed 100644 --- a/llvm/lib/Target/SparcV9/SparcV9.td +++ b/llvm/lib/Target/SparcV9/SparcV9.td @@ -24,7 +24,6 @@ class InstV9 : Instruction { // SparcV9 instruction baseline field bits<32> Inst; let Namespace = "V9"; - let ClassPrefix = "SparcV9"; bits<2> op; let Inst{31-30} = op; // Top two bits are the 'op' field diff --git a/llvm/lib/Target/Target.td b/llvm/lib/Target/Target.td index 6fada3452e6..e111f85d0f0 100644 --- a/llvm/lib/Target/Target.td +++ b/llvm/lib/Target/Target.td @@ -108,7 +108,6 @@ class RegisterClass<ValueType regType, int alignment, list<Register> regList> { class Instruction { string Name = ""; // The opcode string for this instruction string Namespace = ""; - string ClassPrefix = ""; dag OperandList; // An dag containing the MI operand list. string AsmString = ""; // The .s format to print the instruction with. |
