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authorMarek Olsak <marek.olsak@amd.com>2015-02-18 22:12:41 +0000
committerMarek Olsak <marek.olsak@amd.com>2015-02-18 22:12:41 +0000
commit8eeebcccb54906ed9f76b633adeb78a0254cd84c (patch)
treed14081fed6936065191b1d6c8b0fcbcee7bf68cf /llvm/lib/Target
parentb8c818337dc1066731c2eabe84054ccb2df43b90 (diff)
downloadbcm5719-llvm-8eeebcccb54906ed9f76b633adeb78a0254cd84c.tar.gz
bcm5719-llvm-8eeebcccb54906ed9f76b633adeb78a0254cd84c.zip
R600/SI: Simplify verification of AMDGPU::OPERAND_REG_INLINE_C
llvm-svn: 229751
Diffstat (limited to 'llvm/lib/Target')
-rw-r--r--llvm/lib/Target/R600/SIInstrInfo.cpp14
1 files changed, 6 insertions, 8 deletions
diff --git a/llvm/lib/Target/R600/SIInstrInfo.cpp b/llvm/lib/Target/R600/SIInstrInfo.cpp
index 3ca48c8316b..32daeaed35e 100644
--- a/llvm/lib/Target/R600/SIInstrInfo.cpp
+++ b/llvm/lib/Target/R600/SIInstrInfo.cpp
@@ -1151,6 +1151,8 @@ bool SIInstrInfo::verifyInstruction(const MachineInstr *MI,
return false;
}
+ int RegClass = Desc.OpInfo[i].RegClass;
+
switch (Desc.OpInfo[i].OperandType) {
case MCOI::OPERAND_REGISTER:
if (MI->getOperand(i).isImm()) {
@@ -1161,13 +1163,10 @@ bool SIInstrInfo::verifyInstruction(const MachineInstr *MI,
case AMDGPU::OPERAND_REG_IMM32:
break;
case AMDGPU::OPERAND_REG_INLINE_C:
- if (MI->getOperand(i).isImm()) {
- int RegClass = Desc.OpInfo[i].RegClass;
- const TargetRegisterClass *RC = RI.getRegClass(RegClass);
- if (!isInlineConstant(MI->getOperand(i), RC->getSize())) {
- ErrInfo = "Illegal immediate value for operand.";
- return false;
- }
+ if (isLiteralConstant(MI->getOperand(i),
+ RI.getRegClass(RegClass)->getSize())) {
+ ErrInfo = "Illegal immediate value for operand.";
+ return false;
}
break;
case MCOI::OPERAND_IMMEDIATE:
@@ -1186,7 +1185,6 @@ bool SIInstrInfo::verifyInstruction(const MachineInstr *MI,
if (!MI->getOperand(i).isReg())
continue;
- int RegClass = Desc.OpInfo[i].RegClass;
if (RegClass != -1) {
unsigned Reg = MI->getOperand(i).getReg();
if (TargetRegisterInfo::isVirtualRegister(Reg))
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