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| author | Artem Belevich <tra@google.com> | 2017-09-07 18:14:32 +0000 |
|---|---|---|
| committer | Artem Belevich <tra@google.com> | 2017-09-07 18:14:32 +0000 |
| commit | 8af4e23d1ee7e93e9bda835be2b97550a13c0737 (patch) | |
| tree | 5510b5995366fd536e9a222f4fbc20af6b34472c /llvm/lib/Target | |
| parent | 9420ec3378b8502434846e84ae14e57652a78279 (diff) | |
| download | bcm5719-llvm-8af4e23d1ee7e93e9bda835be2b97550a13c0737.tar.gz bcm5719-llvm-8af4e23d1ee7e93e9bda835be2b97550a13c0737.zip | |
[CUDA] Added rudimentary support for CUDA-9 and sm_70.
For now CUDA-9 is not included in the list of CUDA versions clang
searches for, so the path to CUDA-9 must be explicitly passed
via --cuda-path=.
On LLVM side NVPTX added sm_70 GPU type which bumps required
PTX version to 6.0, but otherwise is equivalent to sm_62 at the moment.
Differential Revision: https://reviews.llvm.org/D37576
llvm-svn: 312734
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/NVPTX/NVPTX.td | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/llvm/lib/Target/NVPTX/NVPTX.td b/llvm/lib/Target/NVPTX/NVPTX.td index c77ddbc9978..aba37d36359 100644 --- a/llvm/lib/Target/NVPTX/NVPTX.td +++ b/llvm/lib/Target/NVPTX/NVPTX.td @@ -50,6 +50,8 @@ def SM61 : SubtargetFeature<"sm_61", "SmVersion", "61", "Target SM 6.1">; def SM62 : SubtargetFeature<"sm_62", "SmVersion", "62", "Target SM 6.2">; +def SM70 : SubtargetFeature<"sm_70", "SmVersion", "70", + "Target SM 7.0">; def SATOM : SubtargetFeature<"satom", "HasAtomScope", "true", "Atomic operations with scope">; @@ -67,6 +69,8 @@ def PTX43 : SubtargetFeature<"ptx43", "PTXVersion", "43", "Use PTX version 4.3">; def PTX50 : SubtargetFeature<"ptx50", "PTXVersion", "50", "Use PTX version 5.0">; +def PTX60 : SubtargetFeature<"ptx60", "PTXVersion", "60", + "Use PTX version 6.0">; //===----------------------------------------------------------------------===// // NVPTX supported processors. @@ -87,6 +91,7 @@ def : Proc<"sm_53", [SM53, PTX42]>; def : Proc<"sm_60", [SM60, PTX50, SATOM]>; def : Proc<"sm_61", [SM61, PTX50, SATOM]>; def : Proc<"sm_62", [SM62, PTX50, SATOM]>; +def : Proc<"sm_70", [SM70, PTX60, SATOM]>; def NVPTXInstrInfo : InstrInfo { } |
