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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-01-10 19:08:15 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-01-10 19:08:15 +0000 |
| commit | 8871683d60ce03a271e4ac9c09746a558db8e38f (patch) | |
| tree | 68d8f0a02f109576dd5b9bc24f57434c832e6bbf /llvm/lib/Target | |
| parent | b6d4fa65512b9f195596697ffe7b9fac076dfe36 (diff) | |
| download | bcm5719-llvm-8871683d60ce03a271e4ac9c09746a558db8e38f.tar.gz bcm5719-llvm-8871683d60ce03a271e4ac9c09746a558db8e38f.zip | |
AMDGPU: Add tests for HasMultipleConditionRegisters
This was enabled without many specific tests or the comment.
llvm-svn: 291586
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp index 730bcdcf7af..a700aa85929 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp @@ -434,6 +434,13 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(const TargetMachine &TM, setSchedulingPreference(Sched::RegPressure); setJumpIsExpensive(true); + + // FIXME: This is only partially true. If we have to do vector compares, any + // SGPR pair can be a condition register. If we have a uniform condition, we + // are better off doing SALU operations, where there is only one SCC. For now, + // we don't have a way of knowing during instruction selection if a condition + // will be uniform and we always use vector compares. Assume we are using + // vector compares until that is fixed. setHasMultipleConditionRegisters(true); // SI at least has hardware support for floating point exceptions, but no way |
