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| author | Alex Bradbury <asb@lowrisc.org> | 2017-12-07 12:45:05 +0000 |
|---|---|---|
| committer | Alex Bradbury <asb@lowrisc.org> | 2017-12-07 12:45:05 +0000 |
| commit | 87a54d611042449aff1c8f6ceee417af85dee193 (patch) | |
| tree | 849c061a2c3f06b8df0624632425185aa430a61d /llvm/lib/Target | |
| parent | 1cf9c54e5c74e6e8a5d4cb152b105ab6c5964739 (diff) | |
| download | bcm5719-llvm-87a54d611042449aff1c8f6ceee417af85dee193.tar.gz bcm5719-llvm-87a54d611042449aff1c8f6ceee417af85dee193.zip | |
[RISCV][NFC] Use TargetRegisterClass::hasSubClassEq in storeRegToStackSlot/loadReadFromStackSlot
Simply checking for register class equality will break once additional
register classes are added (as is done for the RVC instruction set extension).
llvm-svn: 320036
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/RISCV/RISCVInstrInfo.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp index 5b4f4fcbb88..186fe363edd 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp @@ -52,7 +52,7 @@ void RISCVInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, if (I != MBB.end()) DL = I->getDebugLoc(); - if (RC == &RISCV::GPRRegClass) + if (RISCV::GPRRegClass.hasSubClassEq(RC)) BuildMI(MBB, I, DL, get(RISCV::SW)) .addReg(SrcReg, getKillRegState(IsKill)) .addFrameIndex(FI) @@ -70,7 +70,7 @@ void RISCVInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, if (I != MBB.end()) DL = I->getDebugLoc(); - if (RC == &RISCV::GPRRegClass) + if (RISCV::GPRRegClass.hasSubClassEq(RC)) BuildMI(MBB, I, DL, get(RISCV::LW), DstReg).addFrameIndex(FI).addImm(0); else llvm_unreachable("Can't load this register from stack slot"); |
