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authorAkira Hatanaka <ahatanaka@mips.com>2012-10-24 02:10:54 +0000
committerAkira Hatanaka <ahatanaka@mips.com>2012-10-24 02:10:54 +0000
commit868b3a333ba6d7a4d6e696d1322f14bdce7c23cc (patch)
tree30a90a810495b29033021db40312f55c6ceccc82 /llvm/lib/Target
parentfad28de40c545b053364528f1aa5864ab289e897 (diff)
downloadbcm5719-llvm-868b3a333ba6d7a4d6e696d1322f14bdce7c23cc.tar.gz
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[mips] Make sure sret argument is returned in register V0.
llvm-svn: 166539
Diffstat (limited to 'llvm/lib/Target')
-rw-r--r--llvm/lib/Target/Mips/MipsISelLowering.cpp5
1 files changed, 3 insertions, 2 deletions
diff --git a/llvm/lib/Target/Mips/MipsISelLowering.cpp b/llvm/lib/Target/Mips/MipsISelLowering.cpp
index 5cc9662864e..91bb0373b70 100644
--- a/llvm/lib/Target/Mips/MipsISelLowering.cpp
+++ b/llvm/lib/Target/Mips/MipsISelLowering.cpp
@@ -3539,10 +3539,11 @@ MipsTargetLowering::LowerReturn(SDValue Chain,
if (!Reg)
llvm_unreachable("sret virtual register not created in the entry block");
SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
+ unsigned V0 = IsN64 ? Mips::V0_64 : Mips::V0;
- Chain = DAG.getCopyToReg(Chain, dl, IsN64 ? Mips::V0_64 : Mips::V0, Val,
- Flag);
+ Chain = DAG.getCopyToReg(Chain, dl, V0, Val, Flag);
Flag = Chain.getValue(1);
+ MF.getRegInfo().addLiveOut(V0);
}
// Return on Mips is always a "jr $ra"
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