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| author | Nate Begeman <natebegeman@mac.com> | 2004-09-27 05:08:17 +0000 |
|---|---|---|
| committer | Nate Begeman <natebegeman@mac.com> | 2004-09-27 05:08:17 +0000 |
| commit | 8656a156cfcd33a1638ce9c815d556c667aef4cc (patch) | |
| tree | 5174b712339e2c159debc5d2621143e5e1c33d53 /llvm/lib/Target | |
| parent | a68d76ebfa9baa979b5baeadf762c871863cc5fa (diff) | |
| download | bcm5719-llvm-8656a156cfcd33a1638ce9c815d556c667aef4cc.tar.gz bcm5719-llvm-8656a156cfcd33a1638ce9c815d556c667aef4cc.zip | |
Correct some BuildMI arguments for the upcoming simple scheduler
llvm-svn: 16519
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPC32ISelSimple.cpp | 2 | ||||
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPC32RegisterInfo.cpp | 2 | ||||
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPC64RegisterInfo.cpp | 2 |
3 files changed, 3 insertions, 3 deletions
diff --git a/llvm/lib/Target/PowerPC/PPC32ISelSimple.cpp b/llvm/lib/Target/PowerPC/PPC32ISelSimple.cpp index 057615d5090..c8fde63e931 100644 --- a/llvm/lib/Target/PowerPC/PPC32ISelSimple.cpp +++ b/llvm/lib/Target/PowerPC/PPC32ISelSimple.cpp @@ -557,7 +557,7 @@ void PPC32ISel::copyGlobalBaseToRegister(MachineBasicBlock *MBB, MachineBasicBlock::iterator MBBI = FirstMBB.begin(); GlobalBaseReg = makeAnotherReg(Type::IntTy); BuildMI(FirstMBB, MBBI, PPC::MovePCtoLR, 0, PPC::LR); - BuildMI(FirstMBB, MBBI, PPC::MFLR, 0, GlobalBaseReg).addReg(PPC::LR); + BuildMI(FirstMBB, MBBI, PPC::MFLR, 1, GlobalBaseReg).addReg(PPC::LR); GlobalBaseInitialized = true; } // Emit our copy of GlobalBaseReg to the destination register in the diff --git a/llvm/lib/Target/PowerPC/PPC32RegisterInfo.cpp b/llvm/lib/Target/PowerPC/PPC32RegisterInfo.cpp index 321a44939b6..a7b5cb5badf 100644 --- a/llvm/lib/Target/PowerPC/PPC32RegisterInfo.cpp +++ b/llvm/lib/Target/PowerPC/PPC32RegisterInfo.cpp @@ -78,7 +78,7 @@ PPC32RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB, unsigned OC = Opcode[getIdx(RC)]; if (SrcReg == PPC::LR) { - BuildMI(MBB, MI, PPC::MFLR, 0, PPC::R11); + BuildMI(MBB, MI, PPC::MFLR, 1, PPC::R11).addReg(PPC::LR); BuildMI(MBB, MI, PPC::IMPLICIT_DEF, 0, PPC::R0); addFrameReference(BuildMI(MBB, MI, OC, 3).addReg(PPC::R11),FrameIdx); } else { diff --git a/llvm/lib/Target/PowerPC/PPC64RegisterInfo.cpp b/llvm/lib/Target/PowerPC/PPC64RegisterInfo.cpp index 1871c2e3152..9375c2c5105 100644 --- a/llvm/lib/Target/PowerPC/PPC64RegisterInfo.cpp +++ b/llvm/lib/Target/PowerPC/PPC64RegisterInfo.cpp @@ -78,7 +78,7 @@ PPC64RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB, const TargetRegisterClass *RC = getRegClass(SrcReg); unsigned OC = Opcode[getIdx(RC)]; if (SrcReg == PPC::LR) { - BuildMI(MBB, MI, PPC::MFLR, 0, PPC::R11); + BuildMI(MBB, MI, PPC::MFLR, 1, PPC::R11).addReg(PPC::LR); BuildMI(MBB, MI, PPC::IMPLICIT_DEF, 0, PPC::R0); addFrameReference(BuildMI(MBB, MI, OC, 3).addReg(PPC::R11),FrameIdx); } else { |
