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authorSimon Pilgrim <llvm-dev@redking.me.uk>2018-10-30 10:32:11 +0000
committerSimon Pilgrim <llvm-dev@redking.me.uk>2018-10-30 10:32:11 +0000
commit858303b827f0cfcc242ed7852cc36b7dd5a0e95c (patch)
tree6214b0a7f678e413bd8a8f97deebc32f97fdc9d7 /llvm/lib/Target
parent4538ed3b85b1b77a1ca4cec1c1dc57a9a0d38fee (diff)
downloadbcm5719-llvm-858303b827f0cfcc242ed7852cc36b7dd5a0e95c.tar.gz
bcm5719-llvm-858303b827f0cfcc242ed7852cc36b7dd5a0e95c.zip
[SelectionDAG] Add FoldBUILD_VECTOR to simplify new BUILD_VECTOR nodes
Similar to FoldCONCAT_VECTORS, this patch adds FoldBUILD_VECTOR to simplify cases that can avoid the creation of the BUILD_VECTOR - if all the operands are UNDEF or if the BUILD_VECTOR simplifies to a copy. This exposed an assumption in some AMDGPU code that getBuildVector was guaranteed to be a BUILD_VECTOR node that I've tried to handle. Differential Revision: https://reviews.llvm.org/D53760 llvm-svn: 345578
Diffstat (limited to 'llvm/lib/Target')
-rw-r--r--llvm/lib/Target/AMDGPU/R600ISelLowering.cpp34
1 files changed, 18 insertions, 16 deletions
diff --git a/llvm/lib/Target/AMDGPU/R600ISelLowering.cpp b/llvm/lib/Target/AMDGPU/R600ISelLowering.cpp
index 8864aabb063..e2a0f05d2b3 100644
--- a/llvm/lib/Target/AMDGPU/R600ISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/R600ISelLowering.cpp
@@ -1685,14 +1685,15 @@ bool R600TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
static SDValue CompactSwizzlableVector(
SelectionDAG &DAG, SDValue VectorEntry,
DenseMap<unsigned, unsigned> &RemapSwizzle) {
- assert(VectorEntry.getOpcode() == ISD::BUILD_VECTOR);
assert(RemapSwizzle.empty());
- SDValue NewBldVec[4] = {
- VectorEntry.getOperand(0),
- VectorEntry.getOperand(1),
- VectorEntry.getOperand(2),
- VectorEntry.getOperand(3)
- };
+
+ SDLoc DL(VectorEntry);
+ EVT EltTy = VectorEntry.getValueType().getVectorElementType();
+
+ SDValue NewBldVec[4];
+ for (unsigned i = 0; i < 4; i++)
+ NewBldVec[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltTy, VectorEntry,
+ DAG.getIntPtrConstant(i, DL));
for (unsigned i = 0; i < 4; i++) {
if (NewBldVec[i].isUndef())
@@ -1727,15 +1728,17 @@ static SDValue CompactSwizzlableVector(
static SDValue ReorganizeVector(SelectionDAG &DAG, SDValue VectorEntry,
DenseMap<unsigned, unsigned> &RemapSwizzle) {
- assert(VectorEntry.getOpcode() == ISD::BUILD_VECTOR);
assert(RemapSwizzle.empty());
- SDValue NewBldVec[4] = {
- VectorEntry.getOperand(0),
- VectorEntry.getOperand(1),
- VectorEntry.getOperand(2),
- VectorEntry.getOperand(3)
- };
- bool isUnmovable[4] = { false, false, false, false };
+
+ SDLoc DL(VectorEntry);
+ EVT EltTy = VectorEntry.getValueType().getVectorElementType();
+
+ SDValue NewBldVec[4];
+ bool isUnmovable[4] = {false, false, false, false};
+ for (unsigned i = 0; i < 4; i++)
+ NewBldVec[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltTy, VectorEntry,
+ DAG.getIntPtrConstant(i, DL));
+
for (unsigned i = 0; i < 4; i++) {
RemapSwizzle[i] = i;
if (NewBldVec[i].getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
@@ -1766,7 +1769,6 @@ static SDValue ReorganizeVector(SelectionDAG &DAG, SDValue VectorEntry,
SDValue R600TargetLowering::OptimizeSwizzle(SDValue BuildVector, SDValue Swz[4],
SelectionDAG &DAG,
const SDLoc &DL) const {
- assert(BuildVector.getOpcode() == ISD::BUILD_VECTOR);
// Old -> New swizzle values
DenseMap<unsigned, unsigned> SwizzleRemap;
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