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| author | Tom Stellard <thomas.stellard@amd.com> | 2014-02-13 23:34:10 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2014-02-13 23:34:10 +0000 |
| commit | 80be9650e36e58c9086f53b8b4b0a2cd2a9e3c75 (patch) | |
| tree | db67378e9abe097a11a72f301ba9480304c7cd2b /llvm/lib/Target | |
| parent | 60b6153044b881799ff54257bda0fd2af3f56f8c (diff) | |
| download | bcm5719-llvm-80be9650e36e58c9086f53b8b4b0a2cd2a9e3c75.tar.gz bcm5719-llvm-80be9650e36e58c9086f53b8b4b0a2cd2a9e3c75.zip | |
R600/SI: Split global vector loads with more than 4 elements
llvm-svn: 201368
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/R600/SIISelLowering.cpp | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/llvm/lib/Target/R600/SIISelLowering.cpp b/llvm/lib/Target/R600/SIISelLowering.cpp index f19aa8efbb4..0d9f34fc4e6 100644 --- a/llvm/lib/Target/R600/SIISelLowering.cpp +++ b/llvm/lib/Target/R600/SIISelLowering.cpp @@ -452,9 +452,11 @@ SDValue SITargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { case ISD::BRCOND: return LowerBRCOND(Op, DAG); case ISD::LOAD: { LoadSDNode *Load = dyn_cast<LoadSDNode>(Op); - if ((Load->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS || - Load->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS) && - Op.getValueType().isVector()) { + if (Op.getValueType().isVector() && + (Load->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS || + Load->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS || + (Load->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS && + Op.getValueType().getVectorNumElements() > 4))) { SDValue MergedValues[2] = { SplitVectorLoad(Op, DAG), Load->getChain() |
