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| author | Tim Renouf <tpr.llvm@botech.co.uk> | 2019-04-18 05:27:01 +0000 |
|---|---|---|
| committer | Tim Renouf <tpr.llvm@botech.co.uk> | 2019-04-18 05:27:01 +0000 |
| commit | 7c55c8d8c347c718dbe359cda064392de5fbf3e7 (patch) | |
| tree | 77d5592e66e789f95fe7c83ba594824d02d8ef13 /llvm/lib/Target | |
| parent | 6263365b082d7e03988a45c113aa3099cabac5de (diff) | |
| download | bcm5719-llvm-7c55c8d8c347c718dbe359cda064392de5fbf3e7.tar.gz bcm5719-llvm-7c55c8d8c347c718dbe359cda064392de5fbf3e7.zip | |
[AMDGPU] Avoid DAG combining assert with fneg(fadd(A,0))
fneg combining attempts to turn it into fadd(fneg(A), fneg(0)), but
creating the new fadd folds to just fneg(A). When A has multiple uses,
this confuses it and you get an assert. Fixed.
Differential Revision: https://reviews.llvm.org/D60633
Change-Id: I0ddc9b7286abe78edc0cd8d734fdeb05ff09821c
llvm-svn: 358640
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp index 623d9817f45..08affa8f057 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp @@ -3692,6 +3692,8 @@ SDValue AMDGPUTargetLowering::performFNegCombine(SDNode *N, RHS = RHS.getOperand(0); SDValue Res = DAG.getNode(ISD::FADD, SL, VT, LHS, RHS, N0->getFlags()); + if (Res.getOpcode() != ISD::FADD) + return SDValue(); // Op got folded away. if (!N0.hasOneUse()) DAG.ReplaceAllUsesWith(N0, DAG.getNode(ISD::FNEG, SL, VT, Res)); return Res; @@ -3711,6 +3713,8 @@ SDValue AMDGPUTargetLowering::performFNegCombine(SDNode *N, RHS = DAG.getNode(ISD::FNEG, SL, VT, RHS); SDValue Res = DAG.getNode(Opc, SL, VT, LHS, RHS, N0->getFlags()); + if (Res.getOpcode() != Opc) + return SDValue(); // Op got folded away. if (!N0.hasOneUse()) DAG.ReplaceAllUsesWith(N0, DAG.getNode(ISD::FNEG, SL, VT, Res)); return Res; @@ -3738,6 +3742,8 @@ SDValue AMDGPUTargetLowering::performFNegCombine(SDNode *N, RHS = RHS.getOperand(0); SDValue Res = DAG.getNode(Opc, SL, VT, LHS, MHS, RHS); + if (Res.getOpcode() != Opc) + return SDValue(); // Op got folded away. if (!N0.hasOneUse()) DAG.ReplaceAllUsesWith(N0, DAG.getNode(ISD::FNEG, SL, VT, Res)); return Res; @@ -3766,6 +3772,8 @@ SDValue AMDGPUTargetLowering::performFNegCombine(SDNode *N, unsigned Opposite = inverseMinMax(Opc); SDValue Res = DAG.getNode(Opposite, SL, VT, NegLHS, NegRHS, N0->getFlags()); + if (Res.getOpcode() != Opposite) + return SDValue(); // Op got folded away. if (!N0.hasOneUse()) DAG.ReplaceAllUsesWith(N0, DAG.getNode(ISD::FNEG, SL, VT, Res)); return Res; @@ -3776,6 +3784,8 @@ SDValue AMDGPUTargetLowering::performFNegCombine(SDNode *N, Ops[I] = DAG.getNode(ISD::FNEG, SL, VT, N0->getOperand(I), N0->getFlags()); SDValue Res = DAG.getNode(AMDGPUISD::FMED3, SL, VT, Ops, N0->getFlags()); + if (Res.getOpcode() != AMDGPUISD::FMED3) + return SDValue(); // Op got folded away. if (!N0.hasOneUse()) DAG.ReplaceAllUsesWith(N0, DAG.getNode(ISD::FNEG, SL, VT, Res)); return Res; |
